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vendor.xilinx_{spartan6,7series}: speedgrade→speed.

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For consistency with ECP5.
This commit is contained in:
whitequark 2019-06-25 15:51:52 +00:00
parent 0a145ed2d9
commit f60ceb349b
2 changed files with 8 additions and 8 deletions
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8
nmigen/vendor/xilinx_7series.py vendored
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@ -42,9 +42,9 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
* ``{{name}}.bit``: binary bitstream. * ``{{name}}.bit``: binary bitstream.
""" """
device = abstractproperty() device = abstractproperty()
package = abstractproperty() package = abstractproperty()
speedgrade = abstractproperty() speed = abstractproperty()
file_templates = { file_templates = {
**TemplatedPlatform.build_script_templates, **TemplatedPlatform.build_script_templates,
@ -54,7 +54,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
""", """,
"{{name}}.tcl": r""" "{{name}}.tcl": r"""
# {{autogenerated}} # {{autogenerated}}
create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speedgrade}} create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
{% for file in platform.extra_files %} {% for file in platform.extra_files %}
{% if file.endswith((".v", ".sv")) -%} {% if file.endswith((".v", ".sv")) -%}
add_files {{file}} add_files {{file}}
@ -63,7 +63,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
add_files {{name}}.v add_files {{name}}.v
read_xdc {{name}}.xdc read_xdc {{name}}.xdc
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}} {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speedgrade}} synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}} {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
report_timing_summary -file {{name}}_timing_synth.rpt report_timing_summary -file {{name}}_timing_synth.rpt
report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt

8
nmigen/vendor/xilinx_spartan6.py vendored
View file

@ -45,9 +45,9 @@ class XilinxSpartan6Platform(TemplatedPlatform):
* ``{{name}}.bit``: binary bitstream. * ``{{name}}.bit``: binary bitstream.
""" """
device = abstractproperty() device = abstractproperty()
package = abstractproperty() package = abstractproperty()
speedgrade = abstractproperty() speed = abstractproperty()
file_templates = { file_templates = {
**TemplatedPlatform.build_script_templates, **TemplatedPlatform.build_script_templates,
@ -70,7 +70,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
-ifn {{name}}.prj -ifn {{name}}.prj
-ofn {{name}}.ngc -ofn {{name}}.ngc
-top {{name}} -top {{name}}
-p {{platform.device}}{{platform.package}}-{{platform.speedgrade}} -p {{platform.device}}{{platform.package}}-{{platform.speed}}
{{get_override("script_after_run")|default("# (script_after_run placeholder)")}} {{get_override("script_after_run")|default("# (script_after_run placeholder)")}}
""", """,
"{{name}}.ucf": r""" "{{name}}.ucf": r"""