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hdl.ir: fix port propagation between siblings, in the other direction.

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This commit is contained in:
whitequark 2018-12-22 00:31:31 +00:00
parent 0df543b204
commit f6772759c8
2 changed files with 26 additions and 5 deletions
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17
nmigen/test/test_hdl_ir.py
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@ -134,6 +134,23 @@ class FragmentPortsTestCase(FHDLTestCase):
f1._propagate_ports(ports=())
self.assertEqual(f1.ports, SignalDict())
def test_output_input_sibling(self):
f1 = Fragment()
f2 = Fragment()
f2.add_statements(
self.c2.eq(0)
)
f2.add_driver(self.c2)
f1.add_subfragment(f2)
f3 = Fragment()
f3.add_statements(
self.c1.eq(self.c2)
)
f1.add_subfragment(f3)
f1._propagate_ports(ports=())
self.assertEqual(f1.ports, SignalDict())
def test_input_cd(self):
sync = ClockDomain()
f = Fragment()