usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity

back.rtlil: infer bit width for instance parameters.

Browse source 
Otherwise, Yosys assumes it is always 32, which is often
inappropriate.
This commit is contained in:
whitequark 2019-11-27 17:58:42 +00:00
parent 56bb42aff2
commit f8428ff505
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
nmigen/back/rtlil.py
View file

@ -128,8 +128,8 @@ class _ModuleBuilder(_Namer, _BufferedBuilder, _AttrBuilder):
self._append(" parameter \\{} \"{}\"\n",
param, value.translate(self._escape_map))
elif isinstance(value, int):
self._append(" parameter \\{} {:d}\n",
param, value)
self._append(" parameter \\{} {}'{:b}\n",
param, bits_for(value), value)
elif isinstance(value, float):
self._append(" parameter real \\{} \"{!r}\"\n",
param, value)