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build.plat,lib.cdc,vendor: unify platform related diagnostics. NFC.

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This commit is contained in:
whitequark 2019-09-24 14:14:45 +00:00
parent 0858b8bf6c
commit f87c00e6c3
3 changed files with 22 additions and 18 deletions
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20
nmigen/build/plat.py
View file

@ -37,7 +37,7 @@ class Platform(ResourceManager, metaclass=ABCMeta):
def default_clk_constraint(self): def default_clk_constraint(self):
if self.default_clk is None: if self.default_clk is None:
raise AttributeError("Platform '{}' does not define a default clock" raise AttributeError("Platform '{}' does not define a default clock"
.format(self.__class__.__name__)) .format(type(self).__name__))
return self.lookup(self.default_clk).clock return self.lookup(self.default_clk).clock
@property @property
@ -45,7 +45,7 @@ class Platform(ResourceManager, metaclass=ABCMeta):
constraint = self.default_clk_constraint constraint = self.default_clk_constraint
if constraint is None: if constraint is None:
raise AttributeError("Platform '{}' does not constrain its default clock" raise AttributeError("Platform '{}' does not constrain its default clock"
.format(self.__class__.__name__)) .format(type(self).__name__))
return constraint.frequency return constraint.frequency
def add_file(self, filename, content): def add_file(self, filename, content):
@ -154,20 +154,20 @@ class Platform(ResourceManager, metaclass=ABCMeta):
""" """
Extract bitstream for fragment ``name`` from ``products`` and download it to a target. Extract bitstream for fragment ``name`` from ``products`` and download it to a target.
""" """
raise NotImplementedError("Platform {} does not support programming" raise NotImplementedError("Platform '{}' does not support programming"
.format(self.__class__.__name__)) .format(type(self).__name__))
def _check_feature(self, feature, pin, attrs, valid_xdrs, valid_attrs): def _check_feature(self, feature, pin, attrs, valid_xdrs, valid_attrs):
if not valid_xdrs: if not valid_xdrs:
raise NotImplementedError("Platform {} does not support {}" raise NotImplementedError("Platform '{}' does not support {}"
.format(self.__class__.__name__, feature)) .format(type(self).__name__, feature))
elif pin.xdr not in valid_xdrs: elif pin.xdr not in valid_xdrs:
raise NotImplementedError("Platform {} does not support {} for XDR {}" raise NotImplementedError("Platform '{}' does not support {} for XDR {}"
.format(self.__class__.__name__, feature, pin.xdr)) .format(type(self).__name__, feature, pin.xdr))
if not valid_attrs and attrs: if not valid_attrs and attrs:
raise NotImplementedError("Platform {} does not support attributes for {}" raise NotImplementedError("Platform '{}' does not support attributes for {}"
.format(self.__class__.__name__, feature)) .format(type(self).__name__, feature))
@staticmethod @staticmethod
def _invert_if(invert, value): def _invert_if(invert, value):

10
nmigen/lib/cdc.py
View file

@ -83,8 +83,9 @@ class FFSynchronizer(Elaboratable):
return platform.get_ff_sync(self) return platform.get_ff_sync(self)
if self._max_input_delay is not None: if self._max_input_delay is not None:
raise NotImplementedError("Platform {!r} does not support constraining input delay " raise NotImplementedError("Platform '{}' does not support constraining input delay "
"for FFSynchronizer".format(platform)) "for FFSynchronizer"
.format(type(platform).__name__))
m = Module() m = Module()
flops = [Signal(self.i.shape(), name="stage{}".format(index), flops = [Signal(self.i.shape(), name="stage{}".format(index),
@ -145,8 +146,9 @@ class ResetSynchronizer(Elaboratable):
return platform.get_reset_sync(self) return platform.get_reset_sync(self)
if self._max_input_delay is not None: if self._max_input_delay is not None:
raise NotImplementedError("Platform {!r} does not support constraining input delay " raise NotImplementedError("Platform '{}' does not support constraining input delay "
"for ResetSynchronizer".format(platform)) "for ResetSynchronizer"
.format(type(platform).__name__))
m = Module() m = Module()
m.domains += ClockDomain("reset_sync", async_reset=True, local=True) m.domains += ClockDomain("reset_sync", async_reset=True, local=True)

10
nmigen/vendor/xilinx_spartan_3_6.py vendored
View file

@ -418,8 +418,9 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
def get_ff_sync(self, ff_sync): def get_ff_sync(self, ff_sync):
if ff_sync._max_input_delay is not None: if ff_sync._max_input_delay is not None:
raise NotImplementedError("Platform {!r} does not support constraining input delay " raise NotImplementedError("Platform '{}' does not support constraining input delay "
"for FFSynchronizer".format(self)) "for FFSynchronizer"
.format(type(self).__name__))
m = Module() m = Module()
flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index), flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index),
@ -433,8 +434,9 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
def get_reset_sync(self, reset_sync): def get_reset_sync(self, reset_sync):
if reset_sync._max_input_delay is not None: if reset_sync._max_input_delay is not None:
raise NotImplementedError("Platform {!r} does not support constraining input delay " raise NotImplementedError("Platform '{}' does not support constraining input delay "
"for ResetSynchronizer".format(self)) "for ResetSynchronizer"
.format(type(self).__name__))
m = Module() m = Module()
m.domains += ClockDomain("reset_sync", async_reset=True, local=True) m.domains += ClockDomain("reset_sync", async_reset=True, local=True)