hdl._ir: Inline AssignmentLegalizer into netlist building.
Fixes #1150.
This commit is contained in:
Wanda
Catherine
parent
3a1f0a7c32
commit
f8e2d26b8f
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@ -10,7 +10,7 @@ from .. import __version__
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from .._toolchain import *
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from ..hdl import *
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from ..hdl._ir import IOBufferInstance, Design
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from ..hdl._xfrm import DomainLowerer, AssignmentLegalizer
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from ..hdl._xfrm import DomainLowerer
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from ..lib.cdc import ResetSynchronizer
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from ..back import rtlil, verilog
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from .res import *
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@ -165,7 +165,6 @@ class Platform(ResourceManager, metaclass=ABCMeta):
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add_pin_fragment(pin, self.get_diff_input_output(pin, port, attrs, invert))
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ports = [(None, signal, None) for signal in self.iter_ports()]
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fragment = AssignmentLegalizer()(fragment)
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fragment = Design(fragment, ports, hierarchy=(name,))
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return self.toolchain_prepare(fragment, name, **kwargs)
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@ -386,7 +386,7 @@ class Fragment:
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return new_ports
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def prepare(self, ports=(), *, hierarchy=("top",), legalize_assignments=False, missing_domain=lambda name: _cd.ClockDomain(name), propagate_domains=True):
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def prepare(self, ports=(), *, hierarchy=("top",), missing_domain=lambda name: _cd.ClockDomain(name), propagate_domains=True):
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from ._xfrm import DomainLowerer
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ports = self._prepare_ports(ports)
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@ -416,9 +416,6 @@ class Fragment:
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]
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fragment = DomainLowerer()(self)
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if legalize_assignments:
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from ._xfrm import AssignmentLegalizer
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fragment = AssignmentLegalizer()(fragment)
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# Create design and let it do the rest.
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return Design(fragment, ports, hierarchy=hierarchy)
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@ -698,10 +695,7 @@ class NetlistEmitter:
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except KeyError:
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pass
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if isinstance(value, _ast.Const):
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result = _nir.Value(
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_nir.Net.from_const((value.value >> bit) & 1)
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for bit in range(value.width)
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)
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result = _nir.Value.from_const(value.value, value.width)
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signed = value.signed
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elif isinstance(value, _ast.Signal):
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result = self.emit_signal(value)
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@ -887,6 +881,95 @@ class NetlistEmitter:
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self.netlist.connections[left] = right
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self.connect_src_loc[left] = src_loc
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def emit_assign(self, module_idx: int, cd: "_cd.ClockDomain | None", lhs: _ast.Value, lhs_start: int, rhs: _nir.Value, cond: _nir.Net, *, src_loc):
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# Assign rhs to lhs[lhs_start:lhs_start+len(rhs)]
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if isinstance(lhs, _ast.Signal):
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if lhs in self.drivers:
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driver = self.drivers[lhs]
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if driver.domain is not cd:
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domain_name = cd.name if cd is not None else "comb"
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other_domain_name = driver.domain.name if driver.domain is not None else "comb"
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raise _ir.DriverConflict(
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f"Signal {lhs} driven from domain {domain_name} at {src_loc} and domain "
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f"{other_domain_name} at {driver.src_loc}")
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if driver.module_idx != module_idx:
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mod_name = ".".join(self.netlist.modules[module_idx].name or ("<toplevel>",))
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other_mod_name = \
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".".join(self.netlist.modules[driver.module_idx].name or ("<toplevel>",))
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raise _ir.DriverConflict(
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f"Signal {lhs} driven from module {mod_name} at {src_loc} and "
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f"module {other_mod_name} at {driver.src_loc}")
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else:
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driver = NetlistDriver(module_idx, lhs, domain=cd, src_loc=src_loc)
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self.drivers[lhs] = driver
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driver.assignments.append(_nir.Assignment(cond=cond, start=lhs_start, value=rhs,
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src_loc=src_loc))
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elif isinstance(lhs, _ast.Slice):
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self.emit_assign(module_idx, cd, lhs.value, lhs_start + lhs.start, rhs, cond, src_loc=src_loc)
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elif isinstance(lhs, _ast.Cat):
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part_stop = 0
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for part in lhs.parts:
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part_start = part_stop
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part_len = len(part)
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part_stop = part_start + part_len
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if lhs_start >= part_stop:
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continue
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if lhs_start + len(rhs) <= part_start:
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continue
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if lhs_start < part_start:
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part_lhs_start = 0
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part_rhs_start = part_start - lhs_start
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else:
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part_lhs_start = lhs_start - part_start
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part_rhs_start = 0
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if lhs_start + len(rhs) >= part_stop:
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part_rhs_stop = part_stop - lhs_start
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else:
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part_rhs_stop = len(rhs)
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self.emit_assign(module_idx, cd, part, part_lhs_start, rhs[part_rhs_start:part_rhs_stop], cond, src_loc=src_loc)
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elif isinstance(lhs, _ast.Part):
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offset, _signed = self.emit_rhs(module_idx, lhs.offset)
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width = len(lhs.value)
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num_cases = min((width + lhs.stride - 1) // lhs.stride, 1 << len(offset))
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conds = []
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for case_index in range(num_cases):
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cell = _nir.Matches(module_idx, value=offset,
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patterns=(f"{case_index:0{len(offset)}b}",),
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src_loc=lhs.src_loc)
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subcond, = self.netlist.add_value_cell(1, cell)
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conds.append(subcond)
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conds = _nir.Value(conds)
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cell = _nir.PriorityMatch(module_idx, en=cond, inputs=conds, src_loc=lhs.src_loc)
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conds = self.netlist.add_value_cell(len(conds), cell)
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for idx, subcond in enumerate(conds):
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start = lhs_start + idx * lhs.stride
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if start >= width:
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continue
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if start + len(rhs) >= width:
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subrhs = rhs[:width - start]
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else:
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subrhs = rhs
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self.emit_assign(module_idx, cd, lhs.value, start, subrhs, subcond, src_loc=src_loc)
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elif isinstance(lhs, _ast.ArrayProxy):
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index, _signed = self.emit_rhs(module_idx, lhs.index)
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conds = []
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for case_index in range(len(lhs.elems)):
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cell = _nir.Matches(module_idx, value=index,
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patterns=(f"{case_index:0{len(index)}b}",),
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src_loc=lhs.src_loc)
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subcond, = self.netlist.add_value_cell(1, cell)
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conds.append(subcond)
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conds = _nir.Value(conds)
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cell = _nir.PriorityMatch(module_idx, en=cond, inputs=conds, src_loc=lhs.src_loc)
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conds = self.netlist.add_value_cell(len(conds), cell)
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for subcond, val in zip(conds, lhs.elems):
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self.emit_assign(module_idx, cd, val, lhs_start, rhs[:len(val)], subcond, src_loc=src_loc)
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elif isinstance(lhs, _ast.Operator):
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assert lhs.operator in ('u', 's')
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self.emit_assign(module_idx, cd, lhs.operands[0], lhs_start, rhs, cond, src_loc=src_loc)
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else:
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assert False # :nocov:
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def emit_stmt(self, module_idx: int, fragment: _ir.Fragment, domain: str,
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stmt: _ast.Statement, cond: _nir.Net):
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if domain == "comb":
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@ -894,42 +977,13 @@ class NetlistEmitter:
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else:
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cd = fragment.domains[domain]
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if isinstance(stmt, _ast.Assign):
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if isinstance(stmt.lhs, _ast.Signal):
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signal = stmt.lhs
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start = 0
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width = signal.width
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elif isinstance(stmt.lhs, _ast.Slice):
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signal = stmt.lhs.value
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start = stmt.lhs.start
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width = stmt.lhs.stop - stmt.lhs.start
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else:
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assert False # :nocov:
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assert isinstance(signal, _ast.Signal)
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if signal in self.drivers:
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driver = self.drivers[signal]
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if driver.domain is not cd:
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domain_name = cd.name if cd is not None else "comb"
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other_domain_name = driver.domain.name if driver.domain is not None else "comb"
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raise _ir.DriverConflict(
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f"Signal {signal} driven from domain {domain_name} at {stmt.src_loc} and domain "
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f"{other_domain_name} at {driver.src_loc}")
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if driver.module_idx != module_idx:
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mod_name = ".".join(self.netlist.modules[module_idx].name or ("<toplevel>",))
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other_mod_name = \
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".".join(self.netlist.modules[driver.module_idx].name or ("<toplevel>",))
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raise _ir.DriverConflict(
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f"Signal {signal} driven from module {mod_name} at {stmt.src_loc} and "
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f"module {other_mod_name} at {driver.src_loc}")
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else:
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driver = NetlistDriver(module_idx, signal, domain=cd, src_loc=stmt.src_loc)
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self.drivers[signal] = driver
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rhs, signed = self.emit_rhs(module_idx, stmt.rhs)
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width = len(stmt.lhs)
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if len(rhs) > width:
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rhs = _nir.Value(rhs[:width])
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if len(rhs) < width:
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rhs = self.extend(rhs, signed, width)
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driver.assignments.append(_nir.Assignment(cond=cond, start=start, value=rhs,
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src_loc=stmt.src_loc))
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self.emit_assign(module_idx, cd, stmt.lhs, 0, rhs, cond, src_loc=stmt.src_loc)
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elif isinstance(stmt, _ast.Property):
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test, _signed = self.emit_rhs(module_idx, stmt.test)
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if len(test) != 1:
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@ -1374,7 +1428,7 @@ def build_netlist(fragment, ports=(), *, name="top", **kwargs):
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if isinstance(fragment, Design):
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design = fragment
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else:
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design = fragment.prepare(ports=ports, hierarchy=(name,), legalize_assignments=True, **kwargs)
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design = fragment.prepare(ports=ports, hierarchy=(name,), **kwargs)
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netlist = _nir.Netlist()
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_emit_netlist(netlist, design)
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netlist.resolve_all_nets()
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@ -88,13 +88,23 @@ class Value(tuple):
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return super().__new__(cls, (nets,))
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return super().__new__(cls, (Net.ensure(net) for net in nets))
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@classmethod
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def from_const(cls, value, width):
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return cls(Net.from_const((value >> bit) & 1) for bit in range(width))
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@classmethod
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def zeros(cls, digits=1):
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return cls(Net.from_const(0) for _ in range(digits))
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return cls.from_const(0, digits)
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@classmethod
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def ones(cls, digits=1):
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return cls(Net.from_const(1) for _ in range(digits))
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return cls.from_const(-1, digits)
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def __getitem__(self, index):
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if isinstance(index, slice):
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return type(self)(super().__getitem__(index))
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else:
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return super().__getitem__(index)
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def __repr__(self):
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pos = 0
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@ -16,7 +16,7 @@ __all__ = ["ValueVisitor", "ValueTransformer",
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"FragmentTransformer",
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"TransformedElaboratable",
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"DomainCollector", "DomainRenamer", "DomainLowerer",
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"ResetInserter", "EnableInserter", "AssignmentLegalizer"]
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"ResetInserter", "EnableInserter"]
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class ValueVisitor(metaclass=ABCMeta):
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@ -603,85 +603,3 @@ class EnableInserter(_ControlInserter):
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if port._domain in self.controls:
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port._en = Mux(self.controls[port._domain], port._en, Const(0, len(port._en)))
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return new_fragment
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class AssignmentLegalizer(FragmentTransformer, StatementTransformer):
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"""Ensures all assignments in switches have one of the following on the LHS:
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- a `Signal`
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- a `Slice` with `value` that is a `Signal`
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"""
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def emit_assign(self, lhs, rhs, lhs_start=0, lhs_stop=None):
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if isinstance(lhs, ArrayProxy):
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# Lower into a switch.
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cases = {}
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for idx, val in enumerate(lhs.elems):
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cases[idx] = self.emit_assign(val, rhs, lhs_start, lhs_stop)
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return [Switch(lhs.index, cases)]
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elif isinstance(lhs, Part):
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offset = lhs.offset
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width = lhs.width
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if lhs_start != 0:
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width -= lhs_start
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if lhs_stop is not None:
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width = lhs_stop - lhs_start
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cases = {}
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lhs_width = len(lhs.value)
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for idx in range(lhs_width):
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start = lhs_start + idx * lhs.stride
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if start >= lhs_width:
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break
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stop = min(start + width, lhs_width)
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cases[idx] = self.emit_assign(lhs.value, rhs, start, stop)
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return [Switch(offset, cases)]
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elif isinstance(lhs, Slice):
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part_start = lhs_start + lhs.start
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if lhs_stop is not None:
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part_stop = lhs_stop + lhs.start
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else:
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part_stop = lhs_start + lhs.stop
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return self.emit_assign(lhs.value, rhs, part_start, part_stop)
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elif isinstance(lhs, Cat):
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# Split into several assignments.
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part_stop = 0
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res = []
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if lhs_stop is None:
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lhs_len = len(lhs) - lhs_start
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else:
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lhs_len = lhs_stop - lhs_start
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if len(rhs) < lhs_len:
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rhs |= Const(0, Shape(lhs_len, signed=rhs.shape().signed))
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for val in lhs.parts:
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part_start = part_stop
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part_len = len(val)
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part_stop = part_start + part_len
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if lhs_start >= part_stop:
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continue
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if lhs_start < part_start:
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part_lhs_start = 0
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part_rhs_start = part_start - lhs_start
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else:
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part_lhs_start = lhs_start - part_start
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part_rhs_start = 0
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if lhs_stop is not None and lhs_stop <= part_start:
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continue
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elif lhs_stop is None or lhs_stop >= part_stop:
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part_lhs_stop = None
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else:
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part_lhs_stop = lhs_stop - part_start
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res += self.emit_assign(val, rhs[part_rhs_start:], part_lhs_start, part_lhs_stop)
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return res
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elif isinstance(lhs, Signal):
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# Already ok.
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if lhs_start != 0 or lhs_stop is not None:
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return [Assign(lhs[lhs_start:lhs_stop], rhs)]
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else:
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return [Assign(lhs, rhs)]
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elif isinstance(lhs, Operator):
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assert lhs.operator in ('u', 's')
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return self.emit_assign(lhs.operands[0], rhs, lhs_start, lhs_stop)
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else:
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raise TypeError
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def on_Assign(self, stmt):
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return self.emit_assign(stmt.lhs, stmt.rhs)
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@ -1059,3 +1059,699 @@ class IOBufferTestCase(FHDLTestCase):
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with self.assertRaisesRegex(ValueError,
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r"^`oe` must not be used if `o` is not used"):
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IOBufferInstance(pad, oe=oe)
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class AssignTestCase(FHDLTestCase):
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def test_simple(self):
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s1 = Signal(8)
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s2 = Signal(8)
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f = Fragment()
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f.add_statements(
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"comb",
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s1.eq(s2)
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)
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f.add_driver(s1, "comb")
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nl = build_netlist(f, ports=[s1, s2])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 's2' 0.2:10)
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(output 's1' 0.2:10)
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)
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(cell 0 0 (top
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(output 's1' 0.2:10)
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(input 's2' 2:10)
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))
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)
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""")
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def test_simple_trunc(self):
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s1 = Signal(8)
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s2 = Signal(10)
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f = Fragment()
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f.add_statements(
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"comb",
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s1.eq(s2)
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)
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f.add_driver(s1, "comb")
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nl = build_netlist(f, ports=[s1, s2])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 's2' 0.2:12)
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(output 's1' 0.2:10)
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)
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(cell 0 0 (top
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(output 's1' 0.2:10)
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(input 's2' 2:12)
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))
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)
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""")
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def test_simple_zext(self):
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s1 = Signal(8)
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s2 = Signal(6)
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f = Fragment()
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f.add_statements(
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"comb",
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s1.eq(s2)
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)
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f.add_driver(s1, "comb")
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nl = build_netlist(f, ports=[s1, s2])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 's2' 0.2:8)
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(output 's1' (cat 0.2:8 2'd0))
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)
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(cell 0 0 (top
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(output 's1' (cat 0.2:8 2'd0))
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(input 's2' 2:8)
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))
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)
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""")
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def test_simple_sext(self):
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s1 = Signal(8)
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s2 = Signal(signed(6))
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f = Fragment()
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f.add_statements(
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"comb",
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s1.eq(s2)
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)
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f.add_driver(s1, "comb")
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nl = build_netlist(f, ports=[s1, s2])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:8)
|
||||
(output 's1' (cat 0.2:8 0.7 0.7))
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' (cat 0.2:8 0.7 0.7))
|
||||
(input 's2' 2:8)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_slice(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1[2:6].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(output 's1' 1.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 1.0:8)
|
||||
(input 's2' 2:6)
|
||||
))
|
||||
(cell 1 0 (assignment_list 8'd0 (1 2:6 0.2:6)))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_part(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1.bit_select(s3, 4).eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(input 's3' 0.6:10)
|
||||
(output 's1' 10.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 10.0:8)
|
||||
(input 's2' 2:6)
|
||||
(input 's3' 6:10)
|
||||
))
|
||||
(cell 1 0 (matches 0.6:10 0000))
|
||||
(cell 2 0 (matches 0.6:10 0001))
|
||||
(cell 3 0 (matches 0.6:10 0010))
|
||||
(cell 4 0 (matches 0.6:10 0011))
|
||||
(cell 5 0 (matches 0.6:10 0100))
|
||||
(cell 6 0 (matches 0.6:10 0101))
|
||||
(cell 7 0 (matches 0.6:10 0110))
|
||||
(cell 8 0 (matches 0.6:10 0111))
|
||||
(cell 9 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0)))
|
||||
(cell 10 0 (assignment_list 8'd0
|
||||
(9.0 0:4 0.2:6)
|
||||
(9.1 1:5 0.2:6)
|
||||
(9.2 2:6 0.2:6)
|
||||
(9.3 3:7 0.2:6)
|
||||
(9.4 4:8 0.2:6)
|
||||
(9.5 5:8 0.2:5)
|
||||
(9.6 6:8 0.2:4)
|
||||
(9.7 7:8 0.2)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_part_short(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(2)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1.bit_select(s3, 4).eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(input 's3' 0.6:8)
|
||||
(output 's1' 6.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 6.0:8)
|
||||
(input 's2' 2:6)
|
||||
(input 's3' 6:8)
|
||||
))
|
||||
(cell 1 0 (matches 0.6:8 00))
|
||||
(cell 2 0 (matches 0.6:8 01))
|
||||
(cell 3 0 (matches 0.6:8 10))
|
||||
(cell 4 0 (matches 0.6:8 11))
|
||||
(cell 5 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0)))
|
||||
(cell 6 0 (assignment_list 8'd0
|
||||
(5.0 0:4 0.2:6)
|
||||
(5.1 1:5 0.2:6)
|
||||
(5.2 2:6 0.2:6)
|
||||
(5.3 3:7 0.2:6)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_part_word(self):
|
||||
s1 = Signal(16)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1.word_select(s3, 4).eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(input 's3' 0.6:10)
|
||||
(output 's1' 6.0:16)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 6.0:16)
|
||||
(input 's2' 2:6)
|
||||
(input 's3' 6:10)
|
||||
))
|
||||
(cell 1 0 (matches 0.6:10 0000))
|
||||
(cell 2 0 (matches 0.6:10 0001))
|
||||
(cell 3 0 (matches 0.6:10 0010))
|
||||
(cell 4 0 (matches 0.6:10 0011))
|
||||
(cell 5 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0)))
|
||||
(cell 6 0 (assignment_list 16'd0
|
||||
(5.0 0:4 0.2:6)
|
||||
(5.1 4:8 0.2:6)
|
||||
(5.2 8:12 0.2:6)
|
||||
(5.3 12:16 0.2:6)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_part_word_misalign(self):
|
||||
s1 = Signal(17)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1.word_select(s3, 4).eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(input 's3' 0.6:10)
|
||||
(output 's1' 7.0:17)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 7.0:17)
|
||||
(input 's2' 2:6)
|
||||
(input 's3' 6:10)
|
||||
))
|
||||
(cell 1 0 (matches 0.6:10 0000))
|
||||
(cell 2 0 (matches 0.6:10 0001))
|
||||
(cell 3 0 (matches 0.6:10 0010))
|
||||
(cell 4 0 (matches 0.6:10 0011))
|
||||
(cell 5 0 (matches 0.6:10 0100))
|
||||
(cell 6 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0)))
|
||||
(cell 7 0 (assignment_list 17'd0
|
||||
(6.0 0:4 0.2:6)
|
||||
(6.1 4:8 0.2:6)
|
||||
(6.2 8:12 0.2:6)
|
||||
(6.3 12:16 0.2:6)
|
||||
(6.4 16:17 0.2)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_concat(self):
|
||||
s1 = Signal(4)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
s4 = Signal(12)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
Cat(s1, s2, s3).eq(s4)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
f.add_driver(s2, "comb")
|
||||
f.add_driver(s3, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3, s4])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's4' 0.2:14)
|
||||
(output 's1' 0.2:6)
|
||||
(output 's2' 0.6:10)
|
||||
(output 's3' 0.10:14)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 0.2:6)
|
||||
(output 's2' 0.6:10)
|
||||
(output 's3' 0.10:14)
|
||||
(input 's4' 2:14)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_concat_narrow(self):
|
||||
s1 = Signal(4)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
s4 = Signal(signed(6))
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
Cat(s1, s2, s3).eq(s4)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
f.add_driver(s2, "comb")
|
||||
f.add_driver(s3, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3, s4])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's4' 0.2:8)
|
||||
(output 's1' 0.2:6)
|
||||
(output 's2' (cat 0.6:8 0.7 0.7))
|
||||
(output 's3' (cat 0.7 0.7 0.7 0.7))
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 0.2:6)
|
||||
(output 's2' (cat 0.6:8 0.7 0.7))
|
||||
(output 's3' (cat 0.7 0.7 0.7 0.7))
|
||||
(input 's4' 2:8)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_operator(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
s3 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements("comb", [
|
||||
s1.as_signed().eq(s3),
|
||||
s2.as_unsigned().eq(s3),
|
||||
])
|
||||
f.add_driver(s1, "comb")
|
||||
f.add_driver(s2, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's3' 0.2:10)
|
||||
(output 's1' 0.2:10)
|
||||
(output 's2' 0.2:10)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 0.2:10)
|
||||
(output 's2' 0.2:10)
|
||||
(input 's3' 2:10)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_array(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
s3 = Signal(8)
|
||||
s4 = Signal(8)
|
||||
s5 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements("comb", [
|
||||
Array([s1, s2, s3])[s4].eq(s5),
|
||||
])
|
||||
f.add_driver(s1, "comb")
|
||||
f.add_driver(s2, "comb")
|
||||
f.add_driver(s3, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3, s4, s5])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's4' 0.2:10)
|
||||
(input 's5' 0.10:18)
|
||||
(output 's1' 5.0:8)
|
||||
(output 's2' 6.0:8)
|
||||
(output 's3' 7.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 5.0:8)
|
||||
(output 's2' 6.0:8)
|
||||
(output 's3' 7.0:8)
|
||||
(input 's4' 2:10)
|
||||
(input 's5' 10:18)
|
||||
))
|
||||
(cell 1 0 (matches 0.2:10 00000000))
|
||||
(cell 2 0 (matches 0.2:10 00000001))
|
||||
(cell 3 0 (matches 0.2:10 00000010))
|
||||
(cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
|
||||
(cell 5 0 (assignment_list 8'd0 (4.0 0:8 0.10:18)))
|
||||
(cell 6 0 (assignment_list 8'd0 (4.1 0:8 0.10:18)))
|
||||
(cell 7 0 (assignment_list 8'd0 (4.2 0:8 0.10:18)))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_sliced_slice(self):
|
||||
s1 = Signal(12)
|
||||
s2 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1[1:11][2:6].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(output 's1' 1.0:12)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 1.0:12)
|
||||
(input 's2' 2:6)
|
||||
))
|
||||
(cell 1 0 (assignment_list 12'd0 (1 3:7 0.2:6)))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_sliced_concat(self):
|
||||
s1 = Signal(4)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
s4 = Signal(4)
|
||||
s5 = Signal(4)
|
||||
s6 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
Cat(s1, s2, s3, s4, s5)[5:14].eq(s6)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
f.add_driver(s2, "comb")
|
||||
f.add_driver(s3, "comb")
|
||||
f.add_driver(s4, "comb")
|
||||
f.add_driver(s5, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3, s4, s5, s6])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's1' 0.2:6)
|
||||
(input 's5' 0.6:10)
|
||||
(input 's6' 0.10:18)
|
||||
(output 's2' 1.0:4)
|
||||
(output 's3' 0.13:17)
|
||||
(output 's4' 2.0:4)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's2' 1.0:4)
|
||||
(output 's3' 0.13:17)
|
||||
(output 's4' 2.0:4)
|
||||
(input 's1' 2:6)
|
||||
(input 's5' 6:10)
|
||||
(input 's6' 10:18)
|
||||
))
|
||||
(cell 1 0 (assignment_list 4'd0 (1 1:4 0.10:13)))
|
||||
(cell 2 0 (assignment_list 4'd0 (1 0:2 (cat 0.17 1'd0))))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_sliced_part(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1.bit_select(s3, 6)[2:4].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(input 's3' 0.6:10)
|
||||
(output 's1' 10.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 10.0:8)
|
||||
(input 's2' 2:6)
|
||||
(input 's3' 6:10)
|
||||
))
|
||||
(cell 1 0 (matches 0.6:10 0000))
|
||||
(cell 2 0 (matches 0.6:10 0001))
|
||||
(cell 3 0 (matches 0.6:10 0010))
|
||||
(cell 4 0 (matches 0.6:10 0011))
|
||||
(cell 5 0 (matches 0.6:10 0100))
|
||||
(cell 6 0 (matches 0.6:10 0101))
|
||||
(cell 7 0 (matches 0.6:10 0110))
|
||||
(cell 8 0 (matches 0.6:10 0111))
|
||||
(cell 9 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0)))
|
||||
(cell 10 0 (assignment_list 8'd0
|
||||
(9.0 2:4 0.2:4)
|
||||
(9.1 3:5 0.2:4)
|
||||
(9.2 4:6 0.2:4)
|
||||
(9.3 5:7 0.2:4)
|
||||
(9.4 6:8 0.2:4)
|
||||
(9.5 7:8 0.2)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_sliced_part_word(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1.word_select(s3, 4)[1:3].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(input 's3' 0.6:10)
|
||||
(output 's1' 4.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 4.0:8)
|
||||
(input 's2' 2:6)
|
||||
(input 's3' 6:10)
|
||||
))
|
||||
(cell 1 0 (matches 0.6:10 0000))
|
||||
(cell 2 0 (matches 0.6:10 0001))
|
||||
(cell 3 0 (priority_match 1 (cat 1.0 2.0)))
|
||||
(cell 4 0 (assignment_list 8'd0
|
||||
(3.0 1:3 0.2:4)
|
||||
(3.1 5:7 0.2:4)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_sliced_array(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
s3 = Signal(8)
|
||||
s4 = Signal(8)
|
||||
s5 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements("comb", [
|
||||
Array([s1, s2, s3])[s4][2:7].eq(s5),
|
||||
])
|
||||
f.add_driver(s1, "comb")
|
||||
f.add_driver(s2, "comb")
|
||||
f.add_driver(s3, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3, s4, s5])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's4' 0.2:10)
|
||||
(input 's5' 0.10:18)
|
||||
(output 's1' 5.0:8)
|
||||
(output 's2' 6.0:8)
|
||||
(output 's3' 7.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 5.0:8)
|
||||
(output 's2' 6.0:8)
|
||||
(output 's3' 7.0:8)
|
||||
(input 's4' 2:10)
|
||||
(input 's5' 10:18)
|
||||
))
|
||||
(cell 1 0 (matches 0.2:10 00000000))
|
||||
(cell 2 0 (matches 0.2:10 00000001))
|
||||
(cell 3 0 (matches 0.2:10 00000010))
|
||||
(cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
|
||||
(cell 5 0 (assignment_list 8'd0 (4.0 2:7 0.10:15)))
|
||||
(cell 6 0 (assignment_list 8'd0 (4.1 2:7 0.10:15)))
|
||||
(cell 7 0 (assignment_list 8'd0 (4.2 2:7 0.10:15)))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_part_slice(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1[1:7].bit_select(s3, 4).eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(input 's3' 0.6:10)
|
||||
(output 's1' 8.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 8.0:8)
|
||||
(input 's2' 2:6)
|
||||
(input 's3' 6:10)
|
||||
))
|
||||
(cell 1 0 (matches 0.6:10 0000))
|
||||
(cell 2 0 (matches 0.6:10 0001))
|
||||
(cell 3 0 (matches 0.6:10 0010))
|
||||
(cell 4 0 (matches 0.6:10 0011))
|
||||
(cell 5 0 (matches 0.6:10 0100))
|
||||
(cell 6 0 (matches 0.6:10 0101))
|
||||
(cell 7 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0 6.0)))
|
||||
(cell 8 0 (assignment_list 8'd0
|
||||
(7.0 1:5 0.2:6)
|
||||
(7.1 2:6 0.2:6)
|
||||
(7.2 3:7 0.2:6)
|
||||
(7.3 4:7 0.2:5)
|
||||
(7.4 5:7 0.2:4)
|
||||
(7.5 6:7 0.2)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_sliced_part_slice(self):
|
||||
s1 = Signal(12)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"comb",
|
||||
s1[3:9].bit_select(s3, 4)[1:3].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's2' 0.2:6)
|
||||
(input 's3' 0.6:10)
|
||||
(output 's1' 8.0:12)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 8.0:12)
|
||||
(input 's2' 2:6)
|
||||
(input 's3' 6:10)
|
||||
))
|
||||
(cell 1 0 (matches 0.6:10 0000))
|
||||
(cell 2 0 (matches 0.6:10 0001))
|
||||
(cell 3 0 (matches 0.6:10 0010))
|
||||
(cell 4 0 (matches 0.6:10 0011))
|
||||
(cell 5 0 (matches 0.6:10 0100))
|
||||
(cell 6 0 (matches 0.6:10 0101))
|
||||
(cell 7 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0 5.0 6.0)))
|
||||
(cell 8 0 (assignment_list 12'd0
|
||||
(7.0 4:6 0.2:4)
|
||||
(7.1 5:7 0.2:4)
|
||||
(7.2 6:8 0.2:4)
|
||||
(7.3 7:9 0.2:4)
|
||||
(7.4 8:9 0.2)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_sliced_operator(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
s3 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements("comb", [
|
||||
s1.as_signed()[2:7].eq(s3),
|
||||
s2.as_unsigned()[2:7].eq(s3),
|
||||
])
|
||||
f.add_driver(s1, "comb")
|
||||
f.add_driver(s2, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's3' 0.2:10)
|
||||
(output 's1' 1.0:8)
|
||||
(output 's2' 2.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(output 's1' 1.0:8)
|
||||
(output 's2' 2.0:8)
|
||||
(input 's3' 2:10)
|
||||
))
|
||||
(cell 1 0 (assignment_list 8'd0 (1 2:7 0.2:7)))
|
||||
(cell 2 0 (assignment_list 8'd0 (1 2:7 0.2:7)))
|
||||
)
|
||||
""")
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
# amaranth: UnusedElaboratable=no
|
||||
|
||||
import warnings
|
||||
|
||||
from amaranth.hdl._ast import *
|
||||
from amaranth.hdl._cd import *
|
||||
from amaranth.hdl._dsl import *
|
||||
|
|
@ -420,329 +418,6 @@ class EnableInserterTestCase(FHDLTestCase):
|
|||
""")
|
||||
|
||||
|
||||
class AssignmentLegalizerTestCase(FHDLTestCase):
|
||||
def test_simple(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
s1.eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((eq (sig s1) (sig s2)))
|
||||
""")
|
||||
|
||||
def test_simple_slice(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
s1[2:6].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((eq (slice (sig s1) 2:6) (sig s2)))
|
||||
""")
|
||||
|
||||
def test_simple_part(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
s1.bit_select(s3, 4).eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((switch (sig s3)
|
||||
(case 0000 (eq (slice (sig s1) 0:4) (sig s2)))
|
||||
(case 0001 (eq (slice (sig s1) 1:5) (sig s2)))
|
||||
(case 0010 (eq (slice (sig s1) 2:6) (sig s2)))
|
||||
(case 0011 (eq (slice (sig s1) 3:7) (sig s2)))
|
||||
(case 0100 (eq (slice (sig s1) 4:8) (sig s2)))
|
||||
(case 0101 (eq (slice (sig s1) 5:8) (sig s2)))
|
||||
(case 0110 (eq (slice (sig s1) 6:8) (sig s2)))
|
||||
(case 0111 (eq (slice (sig s1) 7:8) (sig s2)))
|
||||
))
|
||||
""")
|
||||
|
||||
def test_simple_part_word(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
s1.word_select(s3, 4).eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((switch (sig s3)
|
||||
(case 0000 (eq (slice (sig s1) 0:4) (sig s2)))
|
||||
(case 0001 (eq (slice (sig s1) 4:8) (sig s2)))
|
||||
))
|
||||
""")
|
||||
|
||||
def test_simple_concat(self):
|
||||
s1 = Signal(4)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
s4 = Signal(12)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
Cat(s1, s2, s3).eq(s4)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f.add_driver(s2, "sync")
|
||||
f.add_driver(s3, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s1) (slice (sig s4) 0:12))
|
||||
(eq (sig s2) (slice (sig s4) 4:12))
|
||||
(eq (sig s3) (slice (sig s4) 8:12))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_concat_narrow(self):
|
||||
s1 = Signal(4)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
s4 = Signal(signed(6))
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
Cat(s1, s2, s3).eq(s4)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f.add_driver(s2, "sync")
|
||||
f.add_driver(s3, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s1) (slice (| (sig s4) (const 12'sd0)) 0:12))
|
||||
(eq (sig s2) (slice (| (sig s4) (const 12'sd0)) 4:12))
|
||||
(eq (sig s3) (slice (| (sig s4) (const 12'sd0)) 8:12))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_operator(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
s3 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements("sync", [
|
||||
s1.as_signed().eq(s3),
|
||||
s2.as_unsigned().eq(s3),
|
||||
])
|
||||
f.add_driver(s1, "sync")
|
||||
f.add_driver(s2, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s1) (sig s3))
|
||||
(eq (sig s2) (sig s3))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_simple_array(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
s3 = Signal(8)
|
||||
s4 = Signal(8)
|
||||
s5 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements("sync", [
|
||||
Array([s1, s2, s3])[s4].eq(s5),
|
||||
])
|
||||
f.add_driver(s1, "sync")
|
||||
f.add_driver(s2, "sync")
|
||||
f.add_driver(s3, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((switch (sig s4)
|
||||
(case 00000000 (eq (sig s1) (sig s5)))
|
||||
(case 00000001 (eq (sig s2) (sig s5)))
|
||||
(case 00000010 (eq (sig s3) (sig s5)))
|
||||
))
|
||||
""")
|
||||
|
||||
def test_sliced_slice(self):
|
||||
s1 = Signal(12)
|
||||
s2 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
s1[1:11][2:6].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((eq (slice (sig s1) 3:7) (sig s2)))
|
||||
""")
|
||||
|
||||
def test_sliced_concat(self):
|
||||
s1 = Signal(4)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
s4 = Signal(4)
|
||||
s5 = Signal(4)
|
||||
s6 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
Cat(s1, s2, s3, s4, s5)[5:14].eq(s6)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f.add_driver(s2, "sync")
|
||||
f.add_driver(s3, "sync")
|
||||
f.add_driver(s4, "sync")
|
||||
f.add_driver(s5, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (slice (sig s2) 1:4) (slice (| (sig s6) (const 9'd0)) 0:9))
|
||||
(eq (sig s3) (slice (| (sig s6) (const 9'd0)) 3:9))
|
||||
(eq (slice (sig s4) 0:2) (slice (| (sig s6) (const 9'd0)) 7:9))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_sliced_part(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
s1.bit_select(s3, 4)[1:3].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((switch (sig s3)
|
||||
(case 0000 (eq (slice (sig s1) 1:3) (sig s2)))
|
||||
(case 0001 (eq (slice (sig s1) 2:4) (sig s2)))
|
||||
(case 0010 (eq (slice (sig s1) 3:5) (sig s2)))
|
||||
(case 0011 (eq (slice (sig s1) 4:6) (sig s2)))
|
||||
(case 0100 (eq (slice (sig s1) 5:7) (sig s2)))
|
||||
(case 0101 (eq (slice (sig s1) 6:8) (sig s2)))
|
||||
(case 0110 (eq (slice (sig s1) 7:8) (sig s2)))
|
||||
))
|
||||
""")
|
||||
|
||||
def test_sliced_part_word(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
s1.word_select(s3, 4)[1:3].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((switch (sig s3)
|
||||
(case 0000 (eq (slice (sig s1) 1:3) (sig s2)))
|
||||
(case 0001 (eq (slice (sig s1) 5:7) (sig s2)))
|
||||
))
|
||||
""")
|
||||
|
||||
def test_sliced_array(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
s3 = Signal(8)
|
||||
s4 = Signal(8)
|
||||
s5 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements("sync", [
|
||||
Array([s1, s2, s3])[s4][2:7].eq(s5),
|
||||
])
|
||||
f.add_driver(s1, "sync")
|
||||
f.add_driver(s2, "sync")
|
||||
f.add_driver(s3, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((switch (sig s4)
|
||||
(case 00000000 (eq (slice (sig s1) 2:7) (sig s5)))
|
||||
(case 00000001 (eq (slice (sig s2) 2:7) (sig s5)))
|
||||
(case 00000010 (eq (slice (sig s3) 2:7) (sig s5)))
|
||||
))
|
||||
""")
|
||||
|
||||
def test_part_slice(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
s1[1:7].bit_select(s3, 4).eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((switch (sig s3)
|
||||
(case 0000 (eq (slice (sig s1) 1:5) (sig s2)))
|
||||
(case 0001 (eq (slice (sig s1) 2:6) (sig s2)))
|
||||
(case 0010 (eq (slice (sig s1) 3:7) (sig s2)))
|
||||
(case 0011 (eq (slice (sig s1) 4:7) (sig s2)))
|
||||
(case 0100 (eq (slice (sig s1) 5:7) (sig s2)))
|
||||
(case 0101 (eq (slice (sig s1) 6:7) (sig s2)))
|
||||
))
|
||||
""")
|
||||
|
||||
def test_sliced_part_slice(self):
|
||||
s1 = Signal(12)
|
||||
s2 = Signal(4)
|
||||
s3 = Signal(4)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
s1[3:9].bit_select(s3, 4)[1:3].eq(s2)
|
||||
)
|
||||
f.add_driver(s1, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
((switch (sig s3)
|
||||
(case 0000 (eq (slice (sig s1) 4:6) (sig s2)))
|
||||
(case 0001 (eq (slice (sig s1) 5:7) (sig s2)))
|
||||
(case 0010 (eq (slice (sig s1) 6:8) (sig s2)))
|
||||
(case 0011 (eq (slice (sig s1) 7:9) (sig s2)))
|
||||
(case 0100 (eq (slice (sig s1) 8:9) (sig s2)))
|
||||
))
|
||||
""")
|
||||
|
||||
|
||||
def test_sliced_operator(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
s3 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements("sync", [
|
||||
s1.as_signed()[2:7].eq(s3),
|
||||
s2.as_unsigned()[2:7].eq(s3),
|
||||
])
|
||||
f.add_driver(s1, "sync")
|
||||
f.add_driver(s2, "sync")
|
||||
f = AssignmentLegalizer()(f)
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (slice (sig s1) 2:7) (sig s3))
|
||||
(eq (slice (sig s2) 2:7) (sig s3))
|
||||
)
|
||||
""")
|
||||
|
||||
|
||||
class _MockElaboratable(Elaboratable):
|
||||
def __init__(self):
|
||||
self.s1 = Signal()
|
||||
|
|
|
|||
Loading…
Reference in a new issue