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back.rtlil: handle reset_less domains.

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whitequark 2018-12-16 23:52:47 +00:00
parent 015998eba9
commit f968678937
1 changed files with 2 additions and 1 deletions
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3
nmigen/back/rtlil.py
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@ -515,7 +515,8 @@ def convert_fragment(builder, fragment, name, top):
for domain, _ in fragment.iter_sync(): for domain, _ in fragment.iter_sync():
cd = fragment.domains[domain] cd = fragment.domains[domain]
compiler_state.resolve_curr(cd.clk) compiler_state.resolve_curr(cd.clk)
compiler_state.resolve_curr(cd.rst) if cd.rst is not None:
compiler_state.resolve_curr(cd.rst)
# Transform all subfragments to their respective cells. Transforming signals connected # Transform all subfragments to their respective cells. Transforming signals connected
# to their ports into wires eagerly makes sure they get sensible (prefixed with submodule # to their ports into wires eagerly makes sure they get sensible (prefixed with submodule