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Pyupgrade to 3.8+. NFCI

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This commit is contained in:
Catherine 2023-11-14 12:58:53 +00:00
parent e55dec9615
commit f9da3c0d16
37 changed files with 240 additions and 240 deletions
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24
amaranth/vendor/_gowin.py
View file

@ -86,7 +86,7 @@ class GowinPlatform(TemplatedPlatform):
def _chipdb_device(self):
# GW1NR series does not have its own chipdb file, but works with GW1N
if self.series == "GW1NR":
return "GW1N-{}{}".format(self.size, self.subseries_f)
return f"GW1N-{self.size}{self.subseries_f}"
return self.family
_dev_osc_mapping = {
@ -473,11 +473,11 @@ class GowinPlatform(TemplatedPlatform):
i = o = t = None
if "i" in pin.dir:
i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
i = Signal(pin.width, name=f"{pin.name}_xdr_i")
if "o" in pin.dir:
o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
o = Signal(pin.width, name=f"{pin.name}_xdr_o")
if pin.dir in ("oe", "io"):
t = Signal(1, name="{}_xdr_t".format(pin.name))
t = Signal(1, name=f"{pin.name}_xdr_t")
if pin.xdr == 0:
if "i" in pin.dir:
@ -511,7 +511,7 @@ class GowinPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("IBUF",
i_I=port.io[bit],
o_O=i[bit]
)
@ -523,7 +523,7 @@ class GowinPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, port.io, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("OBUF",
i_I=o[bit],
o_O=port.io[bit]
)
@ -535,7 +535,7 @@ class GowinPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("TBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("TBUF",
i_OEN=t,
i_I=o[bit],
o_O=port.io[bit]
@ -548,7 +548,7 @@ class GowinPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("IOBUF",
i_OEN=t,
i_I=o[bit],
o_O=i[bit],
@ -562,7 +562,7 @@ class GowinPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(pin.wodth):
m.submodules["{}_{}".format(pin.name,bit)] = Instance("TLVDS_IBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("TLVDS_IBUF",
i_I=port.p[bit],
i_IB=port.n[bit],
o_O=i[bit]
@ -575,7 +575,7 @@ class GowinPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name,bit)] = Instance("TLVDS_OBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("TLVDS_OBUF",
i_I=o[bit],
o_O=port.p[bit],
o_OB=port.n[bit],
@ -588,7 +588,7 @@ class GowinPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name,bit)] = Instance("TLVDS_TBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("TLVDS_TBUF",
i_OEN=t,
i_I=o[bit],
o_O=port.p[bit],
@ -602,7 +602,7 @@ class GowinPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name,bit)] = Instance("TLVDS_IOBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("TLVDS_IOBUF",
i_OEN=t,
i_I=o[bit],
o_O=i[bit],

12
amaranth/vendor/_intel.py
View file

@ -323,8 +323,8 @@ class IntelPlatform(TemplatedPlatform):
)
return i_sdr
elif pin.xdr == 2:
i_ddr = Signal(pin.width, name="{}_i_ddr".format(pin.name))
m.submodules["{}_i_ddr".format(pin.name)] = Instance("altddio_in",
i_ddr = Signal(pin.width, name=f"{pin.name}_i_ddr")
m.submodules[f"{pin.name}_i_ddr"] = Instance("altddio_in",
p_width=pin.width,
i_datain=i_ddr,
i_inclock=pin.i_clk,
@ -347,7 +347,7 @@ class IntelPlatform(TemplatedPlatform):
if pin.xdr == 0:
return get_oneg(pin.o)
elif pin.xdr == 1:
o_sdr = Signal(pin.width, name="{}_o_sdr".format(pin.name))
o_sdr = Signal(pin.width, name=f"{pin.name}_o_sdr")
m.submodules += Instance("$dff",
p_CLK_POLARITY=1,
p_WIDTH=pin.width,
@ -357,8 +357,8 @@ class IntelPlatform(TemplatedPlatform):
)
return o_sdr
elif pin.xdr == 2:
o_ddr = Signal(pin.width, name="{}_o_ddr".format(pin.name))
m.submodules["{}_o_ddr".format(pin.name)] = Instance("altddio_out",
o_ddr = Signal(pin.width, name=f"{pin.name}_o_ddr")
m.submodules[f"{pin.name}_o_ddr"] = Instance("altddio_out",
p_width=pin.width,
o_dataout=o_ddr,
i_outclock=pin.o_clk,
@ -374,7 +374,7 @@ class IntelPlatform(TemplatedPlatform):
if pin.xdr == 0:
return pin.oe.replicate(pin.width)
elif pin.xdr in (1, 2):
oe_reg = Signal(pin.width, name="{}_oe_reg".format(pin.name))
oe_reg = Signal(pin.width, name=f"{pin.name}_oe_reg")
oe_reg.attrs["useioff"] = "1"
m.submodules += Instance("$dff",
p_CLK_POLARITY=1,

22
amaranth/vendor/_lattice_ecp5.py
View file

@ -513,11 +513,11 @@ class LatticeECP5Platform(TemplatedPlatform):
i = o = t = None
if "i" in pin.dir:
i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
i = Signal(pin.width, name=f"{pin.name}_xdr_i")
if "o" in pin.dir:
o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
o = Signal(pin.width, name=f"{pin.name}_xdr_o")
if pin.dir in ("oe", "io"):
t = Signal(pin.width, name="{}_xdr_t".format(pin.name))
t = Signal(pin.width, name=f"{pin.name}_xdr_t")
if pin.xdr == 0:
if "i" in pin.dir:
@ -565,7 +565,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
m.submodules[f"{pin.name}_{bit}"] = Instance("IB",
i_I=port.io[bit],
o_O=i[bit]
)
@ -577,7 +577,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
m.submodules[f"{pin.name}_{bit}"] = Instance("OB",
i_I=o[bit],
o_O=port.io[bit]
)
@ -589,7 +589,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ",
i_T=t[bit],
i_I=o[bit],
o_O=port.io[bit]
@ -602,7 +602,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
m.submodules[f"{pin.name}_{bit}"] = Instance("BB",
i_T=t[bit],
i_I=o[bit],
o_O=i[bit],
@ -616,7 +616,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
m.submodules[f"{pin.name}_{bit}"] = Instance("IB",
i_I=port.p[bit],
o_O=i[bit]
)
@ -628,7 +628,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
m.submodules[f"{pin.name}_{bit}"] = Instance("OB",
i_I=o[bit],
o_O=port.p[bit],
)
@ -640,7 +640,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ",
i_T=t[bit],
i_I=o[bit],
o_O=port.p[bit],
@ -653,7 +653,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
m.submodules[f"{pin.name}_{bit}"] = Instance("BB",
i_T=t[bit],
i_I=o[bit],
o_O=i[bit],

10
amaranth/vendor/_lattice_ice40.py
View file

@ -378,7 +378,7 @@ class LatticeICE40Platform(TemplatedPlatform):
m.submodules += Instance("SB_HFOSC",
i_CLKHFEN=1,
i_CLKHFPU=1,
p_CLKHF_DIV="0b{0:02b}".format(self.hfosc_div),
p_CLKHF_DIV=f"0b{self.hfosc_div:02b}",
o_CLKHF=clk_i)
delay = int(100e-6 * self.default_clk_frequency)
# Internal low-speed clock: 10 KHz.
@ -441,7 +441,7 @@ class LatticeICE40Platform(TemplatedPlatform):
def get_ineg(y, invert):
if invert_lut:
a = Signal.like(y, name_suffix="_x{}".format(1 if invert else 0))
a = Signal.like(y, name_suffix=f"_x{1 if invert else 0}")
for bit in range(len(y)):
m.submodules += Instance("SB_LUT4",
p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
@ -460,7 +460,7 @@ class LatticeICE40Platform(TemplatedPlatform):
def get_oneg(a, invert):
if invert_lut:
y = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
y = Signal.like(a, name_suffix=f"_x{1 if invert else 0}")
for bit in range(len(a)):
m.submodules += Instance("SB_LUT4",
p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
@ -566,9 +566,9 @@ class LatticeICE40Platform(TemplatedPlatform):
io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
if is_global_input:
m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_GB_IO", *io_args)
m.submodules[f"{pin.name}_{bit}"] = Instance("SB_GB_IO", *io_args)
else:
m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_IO", *io_args)
m.submodules[f"{pin.name}_{bit}"] = Instance("SB_IO", *io_args)
def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input", pin, attrs,

24
amaranth/vendor/_lattice_machxo_2_3l.py
View file

@ -209,7 +209,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
if osch_freq not in self._supported_osch_freqs:
raise ValueError("Frequency {!r} is not valid for OSCH clock. Valid frequencies are {!r}"
.format(osch_freq, self._supported_osch_freqs))
osch_freq_param = "{:.2f}".format(float(osch_freq))
osch_freq_param = f"{float(osch_freq):.2f}"
m.submodules += [ Instance("OSCH", p_NOM_FREQ=osch_freq_param, i_STDBY=Const(0), o_OSC=clk_i, o_SEDSTDBY=Signal()) ]
# GSR implicitly connects to every appropriate storage element. As such, the sync
# domain is reset-less; domains driven by other clocks would need to have dedicated
@ -308,11 +308,11 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
i = o = t = None
if "i" in pin.dir:
i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
i = Signal(pin.width, name=f"{pin.name}_xdr_i")
if "o" in pin.dir:
o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
o = Signal(pin.width, name=f"{pin.name}_xdr_o")
if pin.dir in ("oe", "io"):
t = Signal(1, name="{}_xdr_t".format(pin.name))
t = Signal(1, name=f"{pin.name}_xdr_t")
if pin.xdr == 0:
if "i" in pin.dir:
@ -350,7 +350,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(len(port)):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
m.submodules[f"{pin.name}_{bit}"] = Instance("IB",
i_I=port.io[bit],
o_O=i[bit]
)
@ -362,7 +362,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(port)):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
m.submodules[f"{pin.name}_{bit}"] = Instance("OB",
i_I=o[bit],
o_O=port.io[bit]
)
@ -374,7 +374,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(len(port)):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=port.io[bit]
@ -387,7 +387,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(len(port)):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
m.submodules[f"{pin.name}_{bit}"] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],
@ -401,7 +401,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
m.submodules[f"{pin.name}_{bit}"] = Instance("IB",
i_I=port.p[bit],
o_O=i[bit]
)
@ -413,7 +413,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
m.submodules[f"{pin.name}_{bit}"] = Instance("OB",
i_I=o[bit],
o_O=port.p[bit],
)
@ -425,7 +425,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=port.p[bit],
@ -438,7 +438,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
m.submodules[f"{pin.name}_{bit}"] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],

44
amaranth/vendor/_xilinx.py
View file

@ -125,9 +125,9 @@ class XilinxPlatform(TemplatedPlatform):
@property
def _part(self):
if self.family in {"ultrascale", "ultrascaleplus"}:
return "{}-{}-{}".format(self.device, self.package, self.speed)
return f"{self.device}-{self.package}-{self.speed}"
else:
return "{}{}-{}".format(self.device, self.package, self.speed)
return f"{self.device}{self.package}-{self.speed}"
@property
def vendor_toolchain(self):
@ -365,7 +365,7 @@ class XilinxPlatform(TemplatedPlatform):
elif self._part.startswith("xc7s"):
return "spartan7"
else:
print("Unknown bitstream device for part {}".format(self._part))
print(f"Unknown bitstream device for part {self._part}")
raise ValueError
# device naming according to part_db.yml of f4pga project
@ -378,7 +378,7 @@ class XilinxPlatform(TemplatedPlatform):
elif self._part.startswith("xc7a200"):
return "xc7a200t_test"
else:
print("Unknown symbiflow device for part {}".format(self._part))
print(f"Unknown symbiflow device for part {self._part}")
raise ValueError
@ -576,7 +576,7 @@ class XilinxPlatform(TemplatedPlatform):
elif device.startswith("xq"):
device = device[2:]
else:
raise ValueError("Device '{}' is not recognized".format(self.device))
raise ValueError(f"Device '{self.device}' is not recognized")
# Do actual name matching.
if device.startswith("2vp"):
self.family = "virtex2p"
@ -635,16 +635,16 @@ class XilinxPlatform(TemplatedPlatform):
assert toolchain in ("Vivado", "ISE", "Symbiflow", "Xray")
if toolchain == "Vivado":
if self.family in ISE_FAMILIES:
raise ValueError("Family '{}' is not supported by the Vivado toolchain, please use ISE instead".format(self.family))
raise ValueError(f"Family '{self.family}' is not supported by the Vivado toolchain, please use ISE instead")
elif toolchain == "ISE":
if self.family not in ISE_FAMILIES and self.family != "series7":
raise ValueError("Family '{}' is not supported by the ISE toolchain, please use Vivado instead".format(self.family))
raise ValueError(f"Family '{self.family}' is not supported by the ISE toolchain, please use Vivado instead")
elif toolchain == "Symbiflow":
if self.family != "series7":
raise ValueError("Family '{}' is not supported by the Symbiflow toolchain".format(self.family))
raise ValueError(f"Family '{self.family}' is not supported by the Symbiflow toolchain")
elif toolchain == "Xray":
if self.family != "series7":
raise ValueError("Family '{}' is not supported by the yosys nextpnr toolchain".format(self.family))
raise ValueError(f"Family '{self.family}' is not supported by the yosys nextpnr toolchain")
self.toolchain = toolchain
@ -926,11 +926,11 @@ class XilinxPlatform(TemplatedPlatform):
i = o = t = None
if "i" in pin.dir:
i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
i = Signal(pin.width, name=f"{pin.name}_xdr_i")
if "o" in pin.dir:
o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
o = Signal(pin.width, name=f"{pin.name}_xdr_o")
if pin.dir in ("oe", "io"):
t = Signal(1, name="{}_xdr_t".format(pin.name))
t = Signal(1, name=f"{pin.name}_xdr_t")
if pin.xdr == 0:
if "i" in pin.dir:
@ -1037,7 +1037,7 @@ class XilinxPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, attrs.get("IOSTANDARD"), i_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("IBUF",
i_I=port.io[bit],
o_O=i[bit]
)
@ -1050,7 +1050,7 @@ class XilinxPlatform(TemplatedPlatform):
i, o, t = self._get_xdr_buffer(m, pin, attrs.get("IOSTANDARD"), o_invert=invert)
if self.vendor_toolchain:
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("OBUF",
i_I=o[bit],
o_O=port.io[bit]
)
@ -1067,7 +1067,7 @@ class XilinxPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, attrs.get("IOSTANDARD"), o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
m.submodules[f"{pin.name}_{bit}"] = Instance("OBUFT",
i_T=t,
i_I=o[bit],
o_O=port.io[bit]
@ -1083,7 +1083,7 @@ class XilinxPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, attrs.get("IOSTANDARD"), i_invert=invert, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
m.submodules[f"{pin.name}_{bit}"] = Instance("IOBUF",
i_T=t,
i_I=o[bit],
o_O=i[bit],
@ -1100,7 +1100,7 @@ class XilinxPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, attrs.get("IOSTANDARD", "LVDS_25"), i_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
m.submodules[f"{pin.name}_{bit}"] = Instance("IBUFDS",
i_I=port.p[bit], i_IB=port.n[bit],
o_O=i[bit]
)
@ -1115,7 +1115,7 @@ class XilinxPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, attrs.get("IOSTANDARD", "LVDS_25"), o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
m.submodules[f"{pin.name}_{bit}"] = Instance("OBUFDS",
i_I=o[bit],
o_O=port.p[bit], o_OB=port.n[bit]
)
@ -1130,7 +1130,7 @@ class XilinxPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, attrs.get("IOSTANDARD", "LVDS_25"), o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
m.submodules[f"{pin.name}_{bit}"] = Instance("OBUFTDS",
i_T=t,
i_I=o[bit],
o_O=port.p[bit], o_OB=port.n[bit]
@ -1146,7 +1146,7 @@ class XilinxPlatform(TemplatedPlatform):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, attrs.get("IOSTANDARD", "LVDS_25"), i_invert=invert, o_invert=invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
m.submodules[f"{pin.name}_{bit}"] = Instance("IOBUFDS",
i_T=t,
i_I=o[bit],
o_O=i[bit],
@ -1168,7 +1168,7 @@ class XilinxPlatform(TemplatedPlatform):
def get_ff_sync(self, ff_sync):
m = Module()
flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index),
flops = [Signal(ff_sync.i.shape(), name=f"stage{index}",
reset=ff_sync._reset, reset_less=ff_sync._reset_less,
attrs={"ASYNC_REG": "TRUE"})
for index in range(ff_sync._stages)]
@ -1190,7 +1190,7 @@ class XilinxPlatform(TemplatedPlatform):
def get_async_ff_sync(self, async_ff_sync):
m = Module()
m.domains += ClockDomain("async_ff", async_reset=True, local=True)
flops = [Signal(1, name="stage{}".format(index), reset=1,
flops = [Signal(1, name=f"stage{index}", reset=1,
attrs={"ASYNC_REG": "TRUE"})
for index in range(async_ff_sync._stages)]
if self.toolchain == "Vivado":