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hdl.ast: Operator.{op→operator}

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Both "operator" and "operand" were shortened to "op" in different
places in code, which caused confusion.
This commit is contained in:
whitequark 2019-10-11 11:37:26 +00:00
parent 7ff4c6ce43
commit fa1e466a65
4 changed files with 72 additions and 66 deletions
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46
nmigen/back/pysim.py
View file

@ -123,64 +123,64 @@ class _RHSValueCompiler(_ValueCompiler):
shape = value.shape()
if len(value.operands) == 1:
arg, = map(self, value.operands)
if value.op == "~":
if value.operator == "~":
return lambda state: normalize(~arg(state), shape)
if value.op == "-":
if value.operator == "-":
return lambda state: normalize(-arg(state), shape)
if value.op == "b":
if value.operator == "b":
return lambda state: normalize(bool(arg(state)), shape)
if value.op == "r|":
if value.operator == "r|":
return lambda state: normalize(arg(state) != 0, shape)
if value.op == "r&":
if value.operator == "r&":
val, = value.operands
mask = (1 << len(val)) - 1
return lambda state: normalize(arg(state) == mask, shape)
if value.op == "r^":
if value.operator == "r^":
# Believe it or not, this is the fastest way to compute a sideways XOR in Python.
return lambda state: normalize(format(arg(state), "b").count("1") % 2, shape)
elif len(value.operands) == 2:
lhs, rhs = map(self, value.operands)
if value.op == "+":
if value.operator == "+":
return lambda state: normalize(lhs(state) + rhs(state), shape)
if value.op == "-":
if value.operator == "-":
return lambda state: normalize(lhs(state) - rhs(state), shape)
if value.op == "*":
if value.operator == "*":
return lambda state: normalize(lhs(state) * rhs(state), shape)
if value.op == "//":
if value.operator == "//":
def floordiv(lhs, rhs):
return 0 if rhs == 0 else lhs // rhs
return lambda state: normalize(floordiv(lhs(state), rhs(state)), shape)
if value.op == "&":
if value.operator == "&":
return lambda state: normalize(lhs(state) & rhs(state), shape)
if value.op == "|":
if value.operator == "|":
return lambda state: normalize(lhs(state) | rhs(state), shape)
if value.op == "^":
if value.operator == "^":
return lambda state: normalize(lhs(state) ^ rhs(state), shape)
if value.op == "<<":
if value.operator == "<<":
def sshl(lhs, rhs):
return lhs << rhs if rhs >= 0 else lhs >> -rhs
return lambda state: normalize(sshl(lhs(state), rhs(state)), shape)
if value.op == ">>":
if value.operator == ">>":
def sshr(lhs, rhs):
return lhs >> rhs if rhs >= 0 else lhs << -rhs
return lambda state: normalize(sshr(lhs(state), rhs(state)), shape)
if value.op == "==":
if value.operator == "==":
return lambda state: normalize(lhs(state) == rhs(state), shape)
if value.op == "!=":
if value.operator == "!=":
return lambda state: normalize(lhs(state) != rhs(state), shape)
if value.op == "<":
if value.operator == "<":
return lambda state: normalize(lhs(state) < rhs(state), shape)
if value.op == "<=":
if value.operator == "<=":
return lambda state: normalize(lhs(state) <= rhs(state), shape)
if value.op == ">":
if value.operator == ">":
return lambda state: normalize(lhs(state) > rhs(state), shape)
if value.op == ">=":
if value.operator == ">=":
return lambda state: normalize(lhs(state) >= rhs(state), shape)
elif len(value.operands) == 3:
if value.op == "m":
if value.operator == "m":
sel, val1, val0 = map(self, value.operands)
return lambda state: val1(state) if sel(state) else val0(state)
raise NotImplementedError("Operator '{}' not implemented".format(value.op)) # :nocov:
raise NotImplementedError("Operator '{}' not implemented".format(value.operator)) # :nocov:
def on_Slice(self, value):
shape = value.shape()

10
nmigen/back/rtlil.py
View file

@ -452,7 +452,7 @@ class _RHSValueCompiler(_ValueCompiler):
arg_bits, arg_sign = arg.shape()
res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits, src=src(value.src_loc))
self.s.rtlil.cell(self.operator_map[(1, value.op)], ports={
self.s.rtlil.cell(self.operator_map[(1, value.operator)], ports={
"\\A": self(arg),
"\\Y": res,
}, params={
@ -485,7 +485,7 @@ class _RHSValueCompiler(_ValueCompiler):
lhs, rhs = value.operands
lhs_bits, lhs_sign = lhs.shape()
rhs_bits, rhs_sign = rhs.shape()
if lhs_sign == rhs_sign or value.op in ("<<", ">>", "**"):
if lhs_sign == rhs_sign or value.operator in ("<<", ">>", "**"):
lhs_wire = self(lhs)
rhs_wire = self(rhs)
else:
@ -494,7 +494,7 @@ class _RHSValueCompiler(_ValueCompiler):
rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits, src=src(value.src_loc))
self.s.rtlil.cell(self.operator_map[(2, value.op)], ports={
self.s.rtlil.cell(self.operator_map[(2, value.operator)], ports={
"\\A": lhs_wire,
"\\B": rhs_wire,
"\\Y": res,
@ -505,7 +505,7 @@ class _RHSValueCompiler(_ValueCompiler):
"B_WIDTH": rhs_bits,
"Y_WIDTH": res_bits,
}, src=src(value.src_loc))
if value.op in ("//", "%"):
if value.operator in ("//", "%"):
# RTLIL leaves division by zero undefined, but we require it to return zero.
divmod_res = res
res = self.s.rtlil.wire(width=res_bits, src=src(value.src_loc))
@ -544,7 +544,7 @@ class _RHSValueCompiler(_ValueCompiler):
elif len(value.operands) == 2:
return self.on_Operator_binary(value)
elif len(value.operands) == 3:
assert value.op == "m"
assert value.operator == "m"
return self.on_Operator_mux(value)
else:
raise TypeError # :nocov: