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hdl.dsl: use private names for FSM ongoing signals

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Thomas Watson 2024-03-23 11:44:44 -05:00 committed by Catherine
parent c7f719ab93
commit fa2adbef84
2 changed files with 14 additions and 15 deletions
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6
amaranth/hdl/_dsl.py
View file

@ -167,7 +167,7 @@ class FSM:
if name not in self.encoding:
self.encoding[name] = len(self.encoding)
fsm_name = self._data["name"]
self._data["ongoing"][name] = Signal(name=f"{fsm_name}_ongoing_{name}")
self._data["ongoing"][name] = Signal(name="")
return self._data["ongoing"][name]
@ -462,7 +462,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
if name not in fsm_data["encoding"]:
fsm_name = fsm_data["name"]
fsm_data["encoding"][name] = len(fsm_data["encoding"])
fsm_data["ongoing"][name] = Signal(name=f"{fsm_name}_ongoing_{name}")
fsm_data["ongoing"][name] = Signal(name="")
try:
_outer_case, self._statements = self._statements, {}
self._ctrl_context = None
@ -486,7 +486,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
if name not in ctrl_data["encoding"]:
fsm_name = ctrl_data["name"]
ctrl_data["encoding"][name] = len(ctrl_data["encoding"])
ctrl_data["ongoing"][name] = Signal(name=f"{fsm_name}_ongoing_{name}")
ctrl_data["ongoing"][name] = Signal(name="")
self._add_statement(
assigns=[FSMNextStatement(ctrl_data, name)],
domain=ctrl_data["domain"],

23
tests/test_hdl_dsl.py
View file

@ -603,8 +603,8 @@ class DSLTestCase(FHDLTestCase):
)
(case 1 )
)
(eq (sig fsm_ongoing_FIRST) (== (sig fsm_state) (const 1'd0)))
(eq (sig fsm_ongoing_SECOND) (== (sig fsm_state) (const 1'd1)))
(eq (sig) (== (sig fsm_state) (const 1'd0)))
(eq (sig) (== (sig fsm_state) (const 1'd1)))
)
""")
self.assertRepr(frag.statements["sync"], """
@ -627,8 +627,7 @@ class DSLTestCase(FHDLTestCase):
"(sig a)": "comb",
"(sig fsm_state)": "sync",
"(sig b)": "sync",
"(sig fsm_ongoing_FIRST)": "comb",
"(sig fsm_ongoing_SECOND)": "comb",
"(sig)": "comb",
})
fsm = frag.find_generated("fsm")
self.assertIsInstance(fsm.state, Signal)
@ -659,8 +658,8 @@ class DSLTestCase(FHDLTestCase):
)
(case 1 )
)
(eq (sig fsm_ongoing_FIRST) (== (sig fsm_state) (const 1'd0)))
(eq (sig fsm_ongoing_SECOND) (== (sig fsm_state) (const 1'd1)))
(eq (sig) (== (sig fsm_state) (const 1'd0)))
(eq (sig) (== (sig fsm_state) (const 1'd1)))
)
""")
self.assertRepr(frag.statements["sync"], """
@ -697,8 +696,8 @@ class DSLTestCase(FHDLTestCase):
)
(case 1 )
)
(eq (sig fsm_ongoing_FIRST) (== (sig fsm_state) (const 1'd0)))
(eq (sig fsm_ongoing_SECOND) (== (sig fsm_state) (const 1'd1)))
(eq (sig) (== (sig fsm_state) (const 1'd0)))
(eq (sig) (== (sig fsm_state) (const 1'd1)))
)
""")
self.assertRepr(frag.statements["sync"], """
@ -743,10 +742,10 @@ class DSLTestCase(FHDLTestCase):
self.maxDiff = 10000
self.assertRepr(frag.statements["comb"], """
(
(eq (sig b) (sig fsm_ongoing_SECOND))
(eq (sig a) (sig fsm_ongoing_FIRST))
(eq (sig fsm_ongoing_SECOND) (== (sig fsm_state) (const 1'd0)))
(eq (sig fsm_ongoing_FIRST) (== (sig fsm_state) (const 1'd1)))
(eq (sig b) (sig))
(eq (sig a) (sig))
(eq (sig) (== (sig fsm_state) (const 1'd0)))
(eq (sig) (== (sig fsm_state) (const 1'd1)))
)
""")