hdl.ast: allow sampling ClockSignal, ResetSignal.

nmigen/hdl/ast.py

@@ -844,7 +844,7 @@ class Sample(Value):
         self.value  = Value.wrap(expr)
         self.clocks = int(clocks)
         self.domain = domain
-        if not isinstance(self.value, (Const, Signal)):
+        if not isinstance(self.value, (Const, Signal, ClockSignal, ResetSignal)):
             raise TypeError("Sampled value may only be a signal or a constant, not {!r}"
                             .format(self.value))
         if self.clocks < 0:

nmigen/hdl/xfrm.py

@@ -364,6 +364,10 @@ class SampleLowerer(FragmentTransformer, ValueTransformer, StatementTransformer)
             return "c${}".format(value.value), value.value
         elif isinstance(value, Signal):
             return "s${}".format(value.name), value.reset
+        elif isinstance(value, ClockSignal):
+            return "clk", 0
+        elif isinstance(value, ResetSignal):
+            return "rst", 1
         else:
             raise NotImplementedError # :nocov: