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hdl.ast: allow sampling ClockSignal, ResetSignal.

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This commit is contained in:
whitequark 2019-01-17 05:23:06 +00:00
parent 8c96675580
commit fa8e876356
3 changed files with 9 additions and 3 deletions
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6
nmigen/test/test_hdl_ast.py
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@ -504,8 +504,10 @@ class SampleTestCase(FHDLTestCase):
self.assertEqual(s.shape(), (1, False))
def test_signal(self):
s = Sample(Signal(2), 1, "sync")
self.assertEqual(s.shape(), (2, False))
s1 = Sample(Signal(2), 1, "sync")
self.assertEqual(s1.shape(), (2, False))
s2 = Sample(ClockSignal(), 1, "sync")
s3 = Sample(ResetSignal(), 1, "sync")
def test_wrong_value_operator(self):
with self.assertRaises(TypeError,