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hdl.ast: allow sampling ClockSignal, ResetSignal.

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whitequark 2019-01-17 05:23:06 +00:00
parent 8c96675580
commit fa8e876356
3 changed files with 9 additions and 3 deletions
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2
nmigen/hdl/ast.py
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@ -844,7 +844,7 @@ class Sample(Value):
self.value = Value.wrap(expr) self.value = Value.wrap(expr)
self.clocks = int(clocks) self.clocks = int(clocks)
self.domain = domain self.domain = domain
if not isinstance(self.value, (Const, Signal)): if not isinstance(self.value, (Const, Signal, ClockSignal, ResetSignal)):
raise TypeError("Sampled value may only be a signal or a constant, not {!r}" raise TypeError("Sampled value may only be a signal or a constant, not {!r}"
.format(self.value)) .format(self.value))
if self.clocks < 0: if self.clocks < 0:

4
nmigen/hdl/xfrm.py
View file

@ -364,6 +364,10 @@ class SampleLowerer(FragmentTransformer, ValueTransformer, StatementTransformer)
return "c${}".format(value.value), value.value return "c${}".format(value.value), value.value
elif isinstance(value, Signal): elif isinstance(value, Signal):
return "s${}".format(value.name), value.reset return "s${}".format(value.name), value.reset
elif isinstance(value, ClockSignal):
return "clk", 0
elif isinstance(value, ResetSignal):
return "rst", 1
else: else:
raise NotImplementedError # :nocov: raise NotImplementedError # :nocov:

6
nmigen/test/test_hdl_ast.py
View file

@ -504,8 +504,10 @@ class SampleTestCase(FHDLTestCase):
self.assertEqual(s.shape(), (1, False)) self.assertEqual(s.shape(), (1, False))
def test_signal(self): def test_signal(self):
s = Sample(Signal(2), 1, "sync") s1 = Sample(Signal(2), 1, "sync")
self.assertEqual(s.shape(), (2, False)) self.assertEqual(s1.shape(), (2, False))
s2 = Sample(ClockSignal(), 1, "sync")
s3 = Sample(ResetSignal(), 1, "sync")
def test_wrong_value_operator(self): def test_wrong_value_operator(self):
with self.assertRaises(TypeError, with self.assertRaises(TypeError,