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build.{res,plat}: propagate extras to pin fragment factories.

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This is necessary because on some platforms, like iCE40, extras
become parameters on an IO primitive, since the constraint file
format is not expressive enough for all of them.
This commit is contained in:
whitequark 2019-06-03 01:58:43 +00:00
parent 268fe6330e
commit fb01854372
3 changed files with 93 additions and 58 deletions
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18
nmigen/test/test_build_res.py
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@ -85,9 +85,9 @@ class ConstraintManagerTestCase(FHDLTestCase):
self.assertEqual(ports[1].name, "i2c_0__sda_io")
self.assertEqual(ports[1].nbits, 1)
self.assertEqual(self.cm._se_pins, [
(i2c.scl, scl),
(i2c.sda, sda),
self.assertEqual(list(self.cm.iter_single_ended_pins()), [
(i2c.scl, scl, {}),
(i2c.sda, sda, {}),
])
self.assertEqual(list(self.cm.iter_port_constraints()), [
("i2c_0__scl_io", ["N10"], {}),
@ -108,12 +108,18 @@ class ConstraintManagerTestCase(FHDLTestCase):
self.assertEqual(n.name, "clk100_0_n")
self.assertEqual(n.nbits, clk100.width)
self.assertEqual(self.cm._dp_pins, [
(clk100, p, n),
self.assertEqual(list(self.cm.iter_differential_pins()), [
(clk100, p, n, {}),
])
self.assertEqual(list(self.cm.iter_port_constraints()), [
("clk100_0_p", ["H1"], {}),
("clk100_0_n", ["H2"], {})
("clk100_0_n", ["H2"], {}),
])
self.assertEqual(list(self.cm.iter_port_constraints(diff_pins="p")), [
("clk100_0_p", ["H1"], {}),
])
self.assertEqual(list(self.cm.iter_port_constraints(diff_pins="n")), [
("clk100_0_n", ["H2"], {}),
])
def test_add_clock(self):