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back.pysim: new simulator backend (WIP).

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This commit is contained in:
whitequark 2018-12-13 18:00:05 +00:00
parent 71f1f717c4
commit fb27c2520b
9 changed files with 437 additions and 17 deletions
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7
examples/clkdiv.py
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@ -1,5 +1,5 @@
from nmigen.fhdl import *
from nmigen.back import rtlil, verilog
from nmigen.back import rtlil, verilog, pysim
class ClockDivisor:
@ -16,5 +16,10 @@ class ClockDivisor:
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[ctr.o]))
print(verilog.convert(frag, ports=[ctr.o]))
sim = pysim.Simulator(frag, vcd_file=open("clkdiv.vcd", "w"))
sim.add_clock("sync", 1e-6)
with sim: sim.run_until(100e-6, run_passive=True)