parent
f9da3c0d16
commit
fc06dd7644
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@ -1,5 +1,3 @@
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import warnings
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from .._toolchain.yosys import *
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from .._toolchain.yosys import *
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from ..hdl import ast, ir
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from ..hdl import ast, ir
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from ..lib import wiring
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from ..lib import wiring
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@ -11,15 +9,11 @@ __all__ = ["YosysError", "convert", "convert_fragment"]
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def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
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def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
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# this version requirement needs to be synchronized with the one in pyproject.toml!
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# this version requirement needs to be synchronized with the one in pyproject.toml!
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yosys = find_yosys(lambda ver: ver >= (0, 10))
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yosys = find_yosys(lambda ver: ver >= (0, 35))
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yosys_version = yosys.version()
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script = []
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script = []
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script.append(f"read_ilang <<rtlil\n{rtlil_text}\nrtlil")
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script.append(f"read_ilang <<rtlil\n{rtlil_text}\nrtlil")
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if yosys_version >= (0, 17):
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script.append("proc -nomux -norom")
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script.append("proc -nomux -norom")
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else:
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script.append("proc -nomux")
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script.append("memory_collect")
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script.append("memory_collect")
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if strip_internal_attrs:
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if strip_internal_attrs:
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@ -20,7 +20,7 @@ dependencies = [
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[project.optional-dependencies]
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[project.optional-dependencies]
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# this version requirement needs to be synchronized with the one in amaranth.back.verilog!
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# this version requirement needs to be synchronized with the one in amaranth.back.verilog!
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builtin-yosys = ["amaranth-yosys>=0.10"]
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builtin-yosys = ["amaranth-yosys>=0.35"]
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remote-build = ["paramiko~=2.7"]
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remote-build = ["paramiko~=2.7"]
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[project.scripts]
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[project.scripts]
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