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back.rtlil: always output negative values as two's complement.

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- is valid in RTLIL but means something entirely different.
This commit is contained in:
whitequark 2018-12-24 01:38:32 +00:00
parent 5702767263
commit fc0fb9d89f
1 changed files with 2 additions and 1 deletions
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3
nmigen/back/rtlil.py
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@ -361,7 +361,8 @@ class _RHSValueCompiler(_ValueCompiler):
if isinstance(value.value, str):
return "{}'{}".format(value.nbits, value.value)
else:
return "{}'{:0{}b}".format(value.nbits, value.value, value.nbits)
value_twos_compl = value.value & ((1 << value.nbits) - 1)
return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits)
def on_Signal(self, value):
wire_curr, wire_next = self.s.resolve(value)