hdl._xfrm: Simplify EnableInserter logic.

amaranth/hdl/_xfrm.py

@@ -575,23 +575,14 @@ class ResetInserter(_ControlInserter):
         fragment.add_statements(domain, Switch(self.controls[domain], {1: stmts}, src_loc=self.src_loc))
 
 
-class _PropertyEnableInserter(StatementTransformer):
-    def __init__(self, en):
-        self.en = en
-
-    def on_Property(self, stmt):
-        return Switch(
-            self.en,
-            {1: [stmt]},
-            src_loc=stmt.src_loc,
-        )
-
-
 class EnableInserter(_ControlInserter):
     def _insert_control(self, fragment, domain, signals):
-        stmts = [s.eq(s) for s in signals]
+        if domain in fragment.statements:
-        fragment.add_statements(domain, Switch(self.controls[domain], {0: stmts}, src_loc=self.src_loc))
+            fragment.statements[domain] = _StatementList([Switch(
-        fragment.statements[domain] = _PropertyEnableInserter(self.controls[domain])(fragment.statements[domain])
+                self.controls[domain],
+                {1: fragment.statements[domain]},
+                src_loc=self.src_loc,
+            )])
 
     def on_fragment(self, fragment):
         new_fragment = super().on_fragment(fragment)

tests/test_hdl_xfrm.py

@@ -337,9 +337,8 @@ class EnableInserterTestCase(FHDLTestCase):
         f = EnableInserter(self.c1)(f)
         self.assertRepr(f.statements["sync"], """
         (
-            (eq (sig s1) (const 1'd1))
             (switch (sig c1)
-                (case 0 (eq (sig s1) (sig s1)))
+                (case 1 (eq (sig s1) (const 1'd1)))
             )
         )
         """)
@@ -359,9 +358,8 @@ class EnableInserterTestCase(FHDLTestCase):
         """)
         self.assertRepr(f.statements["pix"], """
         (
-            (eq (sig s2) (const 1'd0))
             (switch (sig c1)
-                (case 0 (eq (sig s2) (sig s2)))
+                (case 1 (eq (sig s2) (const 1'd0)))
             )
         )
         """)
@@ -380,17 +378,15 @@ class EnableInserterTestCase(FHDLTestCase):
         (f2, _, _), = f1.subfragments
         self.assertRepr(f1.statements["sync"], """
         (
-            (eq (sig s1) (const 1'd1))
             (switch (sig c1)
-                (case 0 (eq (sig s1) (sig s1)))
+                (case 1 (eq (sig s1) (const 1'd1)))
             )
         )
         """)
         self.assertRepr(f2.statements["sync"], """
         (
-            (eq (sig s2) (const 1'd1))
             (switch (sig c1)
-                (case 0 (eq (sig s2) (sig s2)))
+                (case 1 (eq (sig s2) (const 1'd1)))
             )
         )
         """)
@@ -451,9 +447,8 @@ class TransformedElaboratableTestCase(FHDLTestCase):
         f = Fragment.get(te2, None)
         self.assertRepr(f.statements["sync"], """
         (
-            (eq (sig s1) (const 1'd1))
             (switch (sig c1)
-                (case 0 (eq (sig s1) (sig s1)))
+                (case 1 (eq (sig s1) (const 1'd1)))
             )
             (switch (sig c2)
                 (case 1 (eq (sig s1) (const 1'd0)))