test_sim: failing test case.
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@ -882,6 +882,19 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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Simulator(m).run()
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self.assertEqual(warns, [])
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def test_large_expr_parser_overflow(self):
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m = Module()
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a = Signal()
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op = a
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for _ in range(50):
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op = (op ^ 1)
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op = op & op
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m.d.comb += a.eq(op)
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Simulator(m)
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class SimulatorRegressionTestCase(FHDLTestCase):
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def test_bug_325(self):
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