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test: remove FHDLTestCase.assertRaisesRegex.

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This method is only there because I misunderstood the documentation
of unittest.
This commit is contained in:
whitequark 2020-07-02 22:49:04 +00:00
parent 8dd28fecc6
commit fd5ee548b6
3 changed files with 6 additions and 14 deletions
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6
nmigen/test/test_hdl_ast.py
View file

@ -764,13 +764,13 @@ class ArrayTestCase(FHDLTestCase):
v1 = a[s1] v1 = a[s1]
v2 = a[s2] v2 = a[s2]
with self.assertRaisesRegex(ValueError, with self.assertRaisesRegex(ValueError,
regex=r"^Array can no longer be mutated after it was indexed with a value at "): r"^Array can no longer be mutated after it was indexed with a value at "):
a[1] = 2 a[1] = 2
with self.assertRaisesRegex(ValueError, with self.assertRaisesRegex(ValueError,
regex=r"^Array can no longer be mutated after it was indexed with a value at "): r"^Array can no longer be mutated after it was indexed with a value at "):
del a[1] del a[1]
with self.assertRaisesRegex(ValueError, with self.assertRaisesRegex(ValueError,
regex=r"^Array can no longer be mutated after it was indexed with a value at "): r"^Array can no longer be mutated after it was indexed with a value at "):
a.insert(1, 2) a.insert(1, 2)
def test_repr(self): def test_repr(self):

6
nmigen/test/test_sim.py
View file

@ -582,7 +582,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
def process(): def process():
nonlocal survived nonlocal survived
with self.assertRaisesRegex(TypeError, with self.assertRaisesRegex(TypeError,
regex=r"Received unsupported command 1 from process .+?"): r"Received unsupported command 1 from process .+?"):
yield 1 yield 1
yield Settle() yield Settle()
survived = True survived = True
@ -774,7 +774,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim.add_clock(1e-6) sim.add_clock(1e-6)
sim.run_until(1e-5) sim.run_until(1e-5)
with self.assertRaisesRegex(ValueError, with self.assertRaisesRegex(ValueError,
regex=r"^Cannot start writing waveforms after advancing simulation time$"): r"^Cannot start writing waveforms after advancing simulation time$"):
with sim.write_vcd(open(os.path.devnull, "wt")): with sim.write_vcd(open(os.path.devnull, "wt")):
pass pass
@ -785,7 +785,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim = Simulator(m) sim = Simulator(m)
sim.add_clock(1e-6) sim.add_clock(1e-6)
with self.assertRaisesRegex(ValueError, with self.assertRaisesRegex(ValueError,
regex=r"^Already writing waveforms to .+$"): r"^Already writing waveforms to .+$"):
with sim.write_vcd(open(os.path.devnull, "wt")): with sim.write_vcd(open(os.path.devnull, "wt")):
with sim.write_vcd(open(os.path.devnull, "wt")): with sim.write_vcd(open(os.path.devnull, "wt")):
pass pass

8
nmigen/test/utils.py
View file

@ -36,14 +36,6 @@ class FHDLTestCase(unittest.TestCase):
# WTF? unittest.assertRaises is completely broken. # WTF? unittest.assertRaises is completely broken.
self.assertEqual(str(cm.exception), msg) self.assertEqual(str(cm.exception), msg)
@contextmanager
def assertRaisesRegex(self, exception, regex=None):
with super().assertRaises(exception) as cm:
yield
if regex is not None:
# unittest.assertRaisesRegex also seems broken...
self.assertRegex(str(cm.exception), regex)
@contextmanager @contextmanager
def assertWarns(self, category, msg=None): def assertWarns(self, category, msg=None):
with warnings.catch_warnings(record=True) as warns: with warnings.catch_warnings(record=True) as warns: