hdl.ir: call back from Fragment.prepare if a clock domain is missing.

See #57.

nmigen/compat/fhdl/verilog.py

@@ -1,6 +1,7 @@
 import warnings
 
 from ...hdl.ir import Fragment
+from ...hdl.cd import ClockDomain
 from ...back import verilog
 from .conv_output import ConvOutput
 
@@ -16,11 +17,14 @@ def convert(fi, ios=None, name="top", special_overrides=dict(),
                       DeprecationWarning, stacklevel=1)
     # TODO: attr_translate
 
+    def missing_domain(name):
+        if create_clock_domains:
+            return ClockDomain(name)
     v_output = verilog.convert(
         fragment=Fragment.get(fi.get_fragment(), platform=None),
         name=name,
         ports=ios or (),
-        ensure_sync_exists=create_clock_domains
+        missing_domain=missing_domain
     )
     output = ConvOutput()
     output.set_main_source(v_output)

nmigen/compat/sim/__init__.py

@@ -1,6 +1,7 @@
 import functools
 import inspect
 from collections.abc import Iterable
+from ...hdl.cd import ClockDomain
 from ...back.pysim import *
 
 
@@ -18,6 +19,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name
 
     if not isinstance(generators, dict):
         generators = {"sync": generators}
+        fragment.domains += ClockDomain("sync")
 
     with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
         for domain, period in clocks.items():