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hdl.ir: call back from Fragment.prepare if a clock domain is missing.

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See #57.
This commit is contained in:
whitequark 2019-08-03 14:54:20 +00:00
parent ace2b5ff0a
commit fdb0c5a6bc
7 changed files with 116 additions and 18 deletions
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10
nmigen/test/test_hdl_ir.py
View file

@ -376,16 +376,18 @@ class FragmentDomainsTestCase(FHDLTestCase):
f1.add_domains(cd)
f1.add_subfragment(f2)
f1._propagate_domains(ensure_sync_exists=False)
f1._propagate_domains(missing_domain=lambda name: None)
self.assertEqual(f1.domains, {"cd": cd})
self.assertEqual(f2.domains, {"cd": cd})
def test_propagate_ensure_sync(self):
def test_propagate_create_missing(self):
s1 = Signal()
f1 = Fragment()
f1.add_driver(s1, "sync")
f2 = Fragment()
f1.add_subfragment(f2)
f1._propagate_domains(ensure_sync_exists=True)
f1._propagate_domains(missing_domain=lambda name: ClockDomain(name))
self.assertEqual(f1.domains.keys(), {"sync"})
self.assertEqual(f2.domains.keys(), {"sync"})
self.assertEqual(f1.domains["sync"], f2.domains["sync"])
@ -661,7 +663,7 @@ class InstanceTestCase(FHDLTestCase):
f = Fragment()
f.add_subfragment(Instance("foo", o_O=s[0]))
f.add_subfragment(Instance("foo", o_O=s[1]))
fp = f.prepare(ports=[s], ensure_sync_exists=False)
fp = f.prepare(ports=[s], missing_domain=lambda name: None)
self.assertEqual(fp.ports, SignalDict([
(s, "o"),
]))

10
nmigen/test/test_sim.py
View file

@ -385,7 +385,10 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim.add_process(process)
def test_run_until(self):
with self.assertSimulation(Module(), deadline=100e-6) as sim:
m = Module()
s = Signal()
m.d.sync += s.eq(0)
with self.assertSimulation(m, deadline=100e-6) as sim:
sim.add_clock(1e-6)
def process():
for _ in range(101):
@ -401,7 +404,10 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim.add_process(1)
def test_add_clock_wrong(self):
with self.assertSimulation(Module()) as sim:
m = Module()
s = Signal()
m.d.sync += s.eq(0)
with self.assertSimulation(m) as sim:
sim.add_clock(1)
with self.assertRaises(ValueError,
msg="Domain 'sync' already has a clock driving it"):