Commit graph

4 commits

Author SHA1 Message Date
whitequark 8c6c3643cd sim._pyrtl: optimize uses of reflexive operators.
When a literal is used on the left-hand side of a numeric operator,
Python is able to constant-fold some expressions:

    >>> dis.dis(lambda x: 0 + 0 + x)
      1           0 LOAD_CONST               1 (0)
                  2 LOAD_FAST                0 (x)
                  4 BINARY_ADD
                  6 RETURN_VALUE

If a literal is used on the right-hand side such that the left-hand
side is variable, this doesn't happen:

    >>> dis.dis(lambda x: x + 0 + 0)
      1           0 LOAD_FAST                0 (x)
                  2 LOAD_CONST               1 (0)
                  4 BINARY_ADD
                  6 LOAD_CONST               1 (0)
                  8 BINARY_ADD
                 10 RETURN_VALUE

PyRTL generates fairly redundant code due to the pervasive masking,
and because of that, transforming expressions into the former form,
where possible, improves runtime by about 10% on Minerva SRAM SoC.
2020-08-26 13:26:58 +00:00
whitequark cb81618c28 sim._pyrtl: fix miscompilation of -(Const(0b11, 2).as_signed()).
Fixes #473.
2020-08-26 04:15:54 +00:00
whitequark 30e2f91176 sim: simplify. NFC. 2020-07-08 17:31:53 +00:00
whitequark d7a87fef42 back.pysim→sim.pysim; split into more manageable parts.
This is necessary to add cxxrtl as an alternate simulation engine.
2020-07-08 12:49:38 +00:00