5 commits

Author	SHA1	Message	Date
whitequark	378e924280	hdl.ast: rename nbits to width. ... Also, replace `bits, sign = x.shape()` with more idiomatic `width, signed = x.shape()`. This unifies all properties corresponding to `len(x)` to `x.width`. (Not all values have a `width` property.) Fixes #210.	2019-09-20 15:36:25 +00:00
whitequark	94e8f479a5	hdl.mem: use read_port(domain="comb") for asynchronous read ports. ... This avoids the absurdity of the combination of arguments that is read_port(domain="sync", synchronous=True). Fixes #116.	2019-07-01 19:56:49 +00:00
whitequark	58e39f90ce	hdl.mem: coerce memory init values to integers. ... The coercion is carefully chosen to accept (other than normal ints) instances of e.g. np.int64, but reject instances of e.g. float. See https://stackoverflow.com/a/48940855/254415 for details. Fixes #93.	2019-06-11 03:38:44 +00:00
whitequark	d78e6c155b	hdl.mem: add DummyPort, for testing and verification.	2019-01-01 03:08:10 +00:00
whitequark	c49211c76a	hdl.mem: add tests for all error conditions.	2018-12-21 06:07:16 +00:00