whitequark
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92a96e1644
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hdl.rec: add basic record support.
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2018-12-28 13:22:10 +00:00 |
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whitequark
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470d66934f
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hdl.dsl: add support for fsm.ongoing().
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2018-12-27 16:19:01 +00:00 |
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whitequark
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597d778cf6
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examples: add an FSM usage example (UART receiver).
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2018-12-26 10:10:27 +00:00 |
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whitequark
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cf79738744
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cli: new module, for basic design generaton/simulation.
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2018-12-23 00:06:58 +00:00 |
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whitequark
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a061bfaa6c
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hdl.mem: tie rdport.en high for asynchronous or transparent ports.
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2018-12-21 04:22:16 +00:00 |
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whitequark
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2b4a8510ca
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back.rtlil: implement memories.
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2018-12-21 01:55:59 +00:00 |
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whitequark
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f7fec804ec
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ir: allow non-Signals in Instance ports.
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2018-12-20 23:40:40 +00:00 |
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whitequark
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c7f9386eab
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fhdl.ir: add black-box fragments, fragment parameters, and Instance.
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2018-12-17 22:55:39 +00:00 |
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whitequark
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850674637a
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back.rtlil: implement Array.
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2018-12-17 01:15:23 +00:00 |
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whitequark
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1adf58f561
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examples: rename clkdiv/ctrl to ctr/ctr_ce.
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2018-12-15 20:42:52 +00:00 |
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whitequark
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b5a1efa0c8
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Move star imports to make from nmigen import * usable.
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2018-12-15 14:20:10 +00:00 |
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whitequark
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9307a31678
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back.pysim: Simulator({gtkw_signals→traces}=).
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2018-12-14 15:23:22 +00:00 |
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whitequark
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dd00b5e2d6
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back.pysim: more general clean-up.
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2018-12-14 12:46:04 +00:00 |
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whitequark
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a10791e160
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back.pysim: if requested, write a gtkw file with a useful preset.
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2018-12-14 08:04:29 +00:00 |
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whitequark
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3bb7a87e0f
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back.pysim: implement "sync processes", like migen.sim generators.
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2018-12-14 05:13:58 +00:00 |
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whitequark
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d791b77cc8
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back.pysim: allow suspending processes until a tick in a domain.
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2018-12-14 04:33:06 +00:00 |
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whitequark
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6a4004ef8d
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back.pysim: fix handling of process termination.
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2018-12-13 18:17:58 +00:00 |
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whitequark
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fb27c2520b
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back.pysim: new simulator backend (WIP).
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2018-12-13 18:02:46 +00:00 |
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whitequark
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bb04c9e0da
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fhdl, back: trace and emit source locations of values.
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2018-12-13 11:44:06 +00:00 |
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whitequark
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72257b6935
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fhdl.ir: implement clock domain propagation.
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2018-12-13 11:01:03 +00:00 |
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whitequark
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932f1912a2
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fhdl.dsl: use less error-prone Switch/Case two-level syntax.
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2018-12-13 07:11:06 +00:00 |
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whitequark
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ad9b45adcd
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fhdl.ir: fix port threading code.
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2018-12-12 13:00:50 +00:00 |
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whitequark
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0fac1f8d0f
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fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
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2018-12-12 12:38:24 +00:00 |
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whitequark
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bc60631d68
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genlib.cdc.MultiReg: pull in from Migen.
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2018-12-12 10:12:35 +00:00 |
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whitequark
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851ed06769
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ClockDomain.{rst→reset}, for consistency with ResetInserter.
nmigen.compat.ClockDomain would alias this, for Migen compatibility.
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2018-12-12 09:49:02 +00:00 |
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whitequark
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4d3258013d
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Initial commit.
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2018-12-12 03:18:44 +00:00 |
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