5 commits

Author	SHA1	Message	Date
Irides	f39ee6e014	docs/changes: document addition of debug_verilog override.	2022-04-06 00:57:19 +00:00
Catherine	64771a065a	Drop support for Python 3.6.	2022-04-04 09:39:28 +00:00
Irides	538c14116c	sim.pysim: use "bench" as a top level root for testbench signals. ... Fixes #561.	2021-12-16 15:46:05 +00:00
Catherine	0169d47365	docs/changes: add simulation-related changes.	2021-12-16 08:04:02 +00:00
Catherine	a6a13dd612	docs: add changelog.	2021-12-13 13:00:10 +00:00