N. Engelhardt
5fd8a796ae
vendor: don't emit duplicate iobuf submodule names.
...
These are no longer allowed after commit 698b005
2019-07-21 07:49:21 +00:00
Alain Péteut
31c54d32ef
vendor.xilinx_7series: generate also binary bitfile.
...
Fixes #139 .
2019-07-07 21:36:32 +00:00
whitequark
146f3cb684
build.plat: source a script with toolchain environment.
...
Fixes #131 .
2019-07-07 00:44:28 +00:00
whitequark
1ee21d2007
build.plat, vendor.*: don't join strings passed as _opts overrides.
...
Right now an array is expected in any _opts overrides, and if it is
actually a string (because it is passed via an environment variable,
usually), awkwardness results as each character is joined with ` `.
Fixes #130 .
2019-07-06 23:09:46 +00:00
Staf Verhaegen
2829d04033
vendor.xilinx_{7series,spartan6}: Support extra VHDL files.
2019-07-04 21:13:33 +00:00
whitequark
33f21628bb
vendor: give names to IO buffer instances.
...
Fixes #123 .
2019-07-03 14:43:03 +00:00
Alain Péteut
20553b1478
build.plat: add iter_extra_files method.
...
* vendor.*: employ iter_extra_files.
2019-07-02 18:25:29 +00:00
Alain Péteut
b67f5cfa65
vendor.xilinx_7series: read extra .xdc files.
2019-07-02 08:23:37 +00:00
whitequark
f60ceb349b
vendor.xilinx_{spartan6,7series}: speedgrade→speed.
...
For consistency with ECP5.
2019-06-25 15:51:52 +00:00
Jean-François Nguyen
b3c5ff7e95
vendor.xilinx_7series: fix IOB packing.
2019-06-17 20:48:46 +00:00
whitequark
3fc5f170e6
vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.
...
Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.
2019-06-17 15:47:56 +00:00
whitequark
2a8e7bc6f2
vendor.xilinx_{7series,spartan6}: cleanup. NFC.
...
Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.
2019-06-17 15:47:56 +00:00
whitequark
8b34602d91
vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly.
...
Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.
2019-06-17 15:47:56 +00:00
Jean-François Nguyen
01a3101fd3
vendor.xilinx_7series: implement inverters.
2019-06-13 15:14:09 +00:00
Jean-François Nguyen
3b303c3334
vendor.xilinx_7series: implement DDR I/O buffers.
2019-06-12 19:55:10 +00:00
whitequark
efb2d773c3
build.{dsl,res,plat}: add PinsN and DiffPairsN.
2019-06-12 14:42:39 +00:00
Jean-François Nguyen
2b3a0e9fa0
vendor.xilinx_7series: fix typos.
2019-06-07 07:33:20 +00:00
Jean-François Nguyen
f26e612899
vendor.xilinx_7series: implement.
2019-06-06 13:22:15 +00:00
