Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
When a literal is used on the left-hand side of a numeric operator,
Python is able to constant-fold some expressions:
>>> dis.dis(lambda x: 0 + 0 + x)
1 0 LOAD_CONST 1 (0)
2 LOAD_FAST 0 (x)
4 BINARY_ADD
6 RETURN_VALUE
If a literal is used on the right-hand side such that the left-hand
side is variable, this doesn't happen:
>>> dis.dis(lambda x: x + 0 + 0)
1 0 LOAD_FAST 0 (x)
2 LOAD_CONST 1 (0)
4 BINARY_ADD
6 LOAD_CONST 1 (0)
8 BINARY_ADD
10 RETURN_VALUE
PyRTL generates fairly redundant code due to the pervasive masking,
and because of that, transforming expressions into the former form,
where possible, improves runtime by about 10% on Minerva SRAM SoC.
