whitequark
|
3a8685c352
|
Consistently use '{!r}' in and only in TypeError messages.
|
2018-12-15 09:31:58 +00:00 |
|
|
whitequark
|
f9f7921959
|
fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
|
2018-12-15 09:26:36 +00:00 |
|
|
whitequark
|
f5e8c9033d
|
fhdl.ir: fix incorrect uses of positive to say non-negative.
Also test Part and Slice properly.
|
2018-12-15 09:26:23 +00:00 |
|
|
whitequark
|
9010805040
|
compat.fhdl.structure: handle If/Elif with multi-bit condition.
|
2018-12-15 00:10:54 +00:00 |
|
|
whitequark
|
ecea721f43
|
compat.fhdl.module: allow adding native submodules to compat modules.
|
2018-12-14 23:56:50 +00:00 |
|
|
whitequark
|
1c7b43ea49
|
Fix deprecations in Python 3.7.
|
2018-12-14 23:56:50 +00:00 |
|
|
whitequark
|
7108111ad0
|
back.pysim: preserve process locations through add_sync_process().
|
2018-12-14 23:27:36 +00:00 |
|
|
whitequark
|
c4ba5a3915
|
fhdl.ast: clean up stub error messages. NFC.
|
2018-12-14 23:07:16 +00:00 |
|
|
whitequark
|
2001359b66
|
fhdl.ir: automatically flatten hierarchy to resolve driver conflicts.
Fixes #5.
|
2018-12-14 22:48:17 +00:00 |
|
|
whitequark
|
579feaba4e
|
fhdl.ir: Fragment.{drive→add_driver}
|
2018-12-14 20:58:29 +00:00 |
|
|
whitequark
|
0015713bfb
|
back.pysim: count delta cycles separately to avoid clock drift.
|
2018-12-14 20:52:41 +00:00 |
|
|
whitequark
|
a6a8703a0e
|
back.pysim: simplify.
|
2018-12-14 20:45:45 +00:00 |
|
|
whitequark
|
7e3cf26cf8
|
back.pysim: revert 70ebc6f2.
|
2018-12-14 19:46:08 +00:00 |
|
|
whitequark
|
71304c9fe7
|
back.pysim: fix implicit boolean conversion.
|
2018-12-14 19:08:06 +00:00 |
|
|
whitequark
|
fe5fb34fae
|
back.pysim: squash one level of hierarchy.
There's really no point in the "top" node.
|
2018-12-14 18:53:21 +00:00 |
|
|
whitequark
|
70ebc6f2c1
|
back.pysim: implement blocking assignment semantics correctly.
|
2018-12-14 18:47:12 +00:00 |
|
|
whitequark
|
120d817123
|
back.pysim: undriven sync signals should return to previous value.
|
2018-12-14 17:25:48 +00:00 |
|
|
whitequark
|
4f5b4a9bf4
|
back.pysim: in simulator sync processes, start by waiting for a tick.
This matches Migen behavior and also makes more sense.
|
2018-12-14 17:05:11 +00:00 |
|
|
whitequark
|
e230383aac
|
back.pysim: make initial phase configurable.
|
2018-12-14 16:46:16 +00:00 |
|
|
whitequark
|
0ef5ced492
|
compat.sim: match clock period.
|
2018-12-14 16:39:52 +00:00 |
|
|
whitequark
|
17d26c8329
|
compat: add run_simulation shim.
|
2018-12-14 16:22:18 +00:00 |
|
|
whitequark
|
88970ee29f
|
pysim.back: fix add_sync_process wrapper to handle signals correctly.
|
2018-12-14 16:21:53 +00:00 |
|
|
whitequark
|
3bc3647380
|
compat.fhdl.module: fix specials.
|
2018-12-14 16:14:08 +00:00 |
|
|
whitequark
|
3b23645fb7
|
compat: add fhdl.specials.TSTriple shim.
|
2018-12-14 16:09:51 +00:00 |
|
|
whitequark
|
7200346249
|
genlib.io: import TSTriple from Migen.
|
2018-12-14 16:09:51 +00:00 |
|
|
whitequark
|
50ba443f92
|
fhdl.ast: fix Switch with constant test.
|
2018-12-14 16:09:51 +00:00 |
|
|
whitequark
|
a0d555a9fc
|
compat: add genlib.cdc.MultiReg shim.
|
2018-12-14 16:01:38 +00:00 |
|
|
whitequark
|
baba47251c
|
compat.fhdl.module: update deprecation messages.
|
2018-12-14 16:01:38 +00:00 |
|
|
whitequark
|
9307a31678
|
back.pysim: Simulator({gtkw_signals→traces}=).
|
2018-12-14 15:23:22 +00:00 |
|
|
whitequark
|
e3f32a1faf
|
back.pysim: better naming. NFC.
|
2018-12-14 15:21:13 +00:00 |
|
|
whitequark
|
68f8dabb29
|
Travis: install pyvcd.
|
2018-12-14 14:47:03 +00:00 |
|
|
whitequark
|
474d46ced8
|
back.pysim: implement most operators and add tests.
|
2018-12-14 14:21:22 +00:00 |
|
|
whitequark
|
d9aaf0114b
|
back.pysim: close .vcd/.gtkw files on context manager exit.
|
2018-12-14 13:59:03 +00:00 |
|
|
whitequark
|
1655b59d1b
|
back.pysim: show more legible names for processes in errors.
|
2018-12-14 13:50:19 +00:00 |
|
|
whitequark
|
625c55a3b8
|
back.pysim: throw exceptions back at processes.
|
2018-12-14 13:43:25 +00:00 |
|
|
whitequark
|
654722ce14
|
back.pysim: add gtkw traces even more robustly.
|
2018-12-14 13:43:08 +00:00 |
|
|
whitequark
|
7d3f7f277a
|
back.pysim: accept (and evaluate) generator functions.
|
2018-12-14 13:32:30 +00:00 |
|
|
whitequark
|
7fc9f98b98
|
back.pysim: skip VCD signal population if VCD is not requested.
|
2018-12-14 13:32:30 +00:00 |
|
|
whitequark
|
3ad79ec690
|
back.pysim: allow processes to evaluate expressions.
|
2018-12-14 13:32:30 +00:00 |
|
|
whitequark
|
151d079f01
|
fhdl.ir: oops, we defined DomainError twice.
|
2018-12-14 12:59:54 +00:00 |
|
|
whitequark
|
dd00b5e2d6
|
back.pysim: more general clean-up.
|
2018-12-14 12:46:04 +00:00 |
|
|
whitequark
|
1b7f8c7950
|
back.pysim: general clean-up.
|
2018-12-14 12:22:03 +00:00 |
|
|
whitequark
|
105113f1d8
|
back.pysim: accept any valid assignments from processes.
|
2018-12-14 12:18:41 +00:00 |
|
|
whitequark
|
240a40c2c2
|
back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
|
2018-12-14 10:57:13 +00:00 |
|
|
whitequark
|
7d91dd56c8
|
fhdl.xfrm: implement DomainLowerer.
|
2018-12-14 10:56:53 +00:00 |
|
|
whitequark
|
b34c1a9ad0
|
back.pysim: undriven comb signals should return to reset value.
|
2018-12-14 09:12:38 +00:00 |
|
|
whitequark
|
b58715c5dc
|
ast, back.pysim: allow specifying user-defined decoders for signals.
|
2018-12-14 09:02:29 +00:00 |
|
|
whitequark
|
bb843cb40c
|
back.pysim: fix completely broken codegen for Switch.
|
2018-12-14 08:51:36 +00:00 |
|
|
whitequark
|
6aefd0c04c
|
back.pysim: raise an exception if delta cycles blow a process deadline.
|
2018-12-14 08:10:21 +00:00 |
|
|
whitequark
|
a10791e160
|
back.pysim: if requested, write a gtkw file with a useful preset.
|
2018-12-14 08:04:29 +00:00 |
|