whitequark
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1f10bd96b9
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Determine Migen's API surface and document compatibility summary.
This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.
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2018-12-15 11:52:30 +00:00 |
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whitequark
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b70340c0da
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pyback.sim: test Slice, Cat, Repl.
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2018-12-15 10:09:14 +00:00 |
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whitequark
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db4600d52b
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fhdl.ast, back.pysim: implement shifts.
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2018-12-15 09:58:30 +00:00 |
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whitequark
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46f5addf05
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fhdl.ast: refactor Operator.shape(). NFC.
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2018-12-15 09:46:20 +00:00 |
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whitequark
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3a8685c352
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Consistently use '{!r}' in and only in TypeError messages.
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2018-12-15 09:31:58 +00:00 |
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whitequark
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f9f7921959
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fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
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2018-12-15 09:26:36 +00:00 |
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whitequark
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f5e8c9033d
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fhdl.ir: fix incorrect uses of positive to say non-negative.
Also test Part and Slice properly.
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2018-12-15 09:26:23 +00:00 |
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whitequark
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9010805040
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compat.fhdl.structure: handle If/Elif with multi-bit condition.
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2018-12-15 00:10:54 +00:00 |
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whitequark
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ecea721f43
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compat.fhdl.module: allow adding native submodules to compat modules.
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2018-12-14 23:56:50 +00:00 |
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whitequark
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1c7b43ea49
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Fix deprecations in Python 3.7.
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2018-12-14 23:56:50 +00:00 |
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whitequark
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7108111ad0
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back.pysim: preserve process locations through add_sync_process().
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2018-12-14 23:27:36 +00:00 |
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whitequark
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c4ba5a3915
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fhdl.ast: clean up stub error messages. NFC.
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2018-12-14 23:07:16 +00:00 |
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whitequark
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2001359b66
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fhdl.ir: automatically flatten hierarchy to resolve driver conflicts.
Fixes #5.
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2018-12-14 22:48:17 +00:00 |
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whitequark
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579feaba4e
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fhdl.ir: Fragment.{drive→add_driver}
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2018-12-14 20:58:29 +00:00 |
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whitequark
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0015713bfb
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back.pysim: count delta cycles separately to avoid clock drift.
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2018-12-14 20:52:41 +00:00 |
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whitequark
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a6a8703a0e
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back.pysim: simplify.
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2018-12-14 20:45:45 +00:00 |
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whitequark
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7e3cf26cf8
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back.pysim: revert 70ebc6f2.
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2018-12-14 19:46:08 +00:00 |
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whitequark
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71304c9fe7
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back.pysim: fix implicit boolean conversion.
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2018-12-14 19:08:06 +00:00 |
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whitequark
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fe5fb34fae
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back.pysim: squash one level of hierarchy.
There's really no point in the "top" node.
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2018-12-14 18:53:21 +00:00 |
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whitequark
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70ebc6f2c1
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back.pysim: implement blocking assignment semantics correctly.
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2018-12-14 18:47:12 +00:00 |
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whitequark
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120d817123
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back.pysim: undriven sync signals should return to previous value.
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2018-12-14 17:25:48 +00:00 |
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whitequark
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4f5b4a9bf4
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back.pysim: in simulator sync processes, start by waiting for a tick.
This matches Migen behavior and also makes more sense.
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2018-12-14 17:05:11 +00:00 |
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whitequark
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e230383aac
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back.pysim: make initial phase configurable.
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2018-12-14 16:46:16 +00:00 |
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whitequark
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0ef5ced492
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compat.sim: match clock period.
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2018-12-14 16:39:52 +00:00 |
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whitequark
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17d26c8329
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compat: add run_simulation shim.
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2018-12-14 16:22:18 +00:00 |
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whitequark
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88970ee29f
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pysim.back: fix add_sync_process wrapper to handle signals correctly.
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2018-12-14 16:21:53 +00:00 |
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whitequark
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3bc3647380
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compat.fhdl.module: fix specials.
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2018-12-14 16:14:08 +00:00 |
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whitequark
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3b23645fb7
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compat: add fhdl.specials.TSTriple shim.
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2018-12-14 16:09:51 +00:00 |
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whitequark
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7200346249
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genlib.io: import TSTriple from Migen.
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2018-12-14 16:09:51 +00:00 |
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whitequark
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50ba443f92
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fhdl.ast: fix Switch with constant test.
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2018-12-14 16:09:51 +00:00 |
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whitequark
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a0d555a9fc
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compat: add genlib.cdc.MultiReg shim.
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2018-12-14 16:01:38 +00:00 |
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whitequark
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baba47251c
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compat.fhdl.module: update deprecation messages.
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2018-12-14 16:01:38 +00:00 |
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whitequark
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9307a31678
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back.pysim: Simulator({gtkw_signals→traces}=).
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2018-12-14 15:23:22 +00:00 |
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whitequark
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e3f32a1faf
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back.pysim: better naming. NFC.
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2018-12-14 15:21:13 +00:00 |
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whitequark
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474d46ced8
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back.pysim: implement most operators and add tests.
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2018-12-14 14:21:22 +00:00 |
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whitequark
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d9aaf0114b
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back.pysim: close .vcd/.gtkw files on context manager exit.
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2018-12-14 13:59:03 +00:00 |
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whitequark
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1655b59d1b
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back.pysim: show more legible names for processes in errors.
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2018-12-14 13:50:19 +00:00 |
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whitequark
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625c55a3b8
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back.pysim: throw exceptions back at processes.
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2018-12-14 13:43:25 +00:00 |
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whitequark
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654722ce14
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back.pysim: add gtkw traces even more robustly.
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2018-12-14 13:43:08 +00:00 |
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whitequark
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7d3f7f277a
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back.pysim: accept (and evaluate) generator functions.
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2018-12-14 13:32:30 +00:00 |
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whitequark
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7fc9f98b98
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back.pysim: skip VCD signal population if VCD is not requested.
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2018-12-14 13:32:30 +00:00 |
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whitequark
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3ad79ec690
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back.pysim: allow processes to evaluate expressions.
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2018-12-14 13:32:30 +00:00 |
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whitequark
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151d079f01
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fhdl.ir: oops, we defined DomainError twice.
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2018-12-14 12:59:54 +00:00 |
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whitequark
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dd00b5e2d6
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back.pysim: more general clean-up.
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2018-12-14 12:46:04 +00:00 |
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whitequark
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1b7f8c7950
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back.pysim: general clean-up.
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2018-12-14 12:22:03 +00:00 |
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whitequark
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105113f1d8
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back.pysim: accept any valid assignments from processes.
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2018-12-14 12:18:41 +00:00 |
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whitequark
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240a40c2c2
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back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
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2018-12-14 10:57:13 +00:00 |
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whitequark
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7d91dd56c8
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fhdl.xfrm: implement DomainLowerer.
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2018-12-14 10:56:53 +00:00 |
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whitequark
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b34c1a9ad0
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back.pysim: undriven comb signals should return to reset value.
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2018-12-14 09:12:38 +00:00 |
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whitequark
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b58715c5dc
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ast, back.pysim: allow specifying user-defined decoders for signals.
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2018-12-14 09:02:29 +00:00 |
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whitequark
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bb843cb40c
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back.pysim: fix completely broken codegen for Switch.
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2018-12-14 08:51:36 +00:00 |
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whitequark
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6aefd0c04c
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back.pysim: raise an exception if delta cycles blow a process deadline.
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2018-12-14 08:10:21 +00:00 |
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whitequark
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a10791e160
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back.pysim: if requested, write a gtkw file with a useful preset.
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2018-12-14 08:04:29 +00:00 |
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whitequark
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cb998d891b
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back.pysim: explain how delta cycles work.
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2018-12-14 07:26:26 +00:00 |
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whitequark
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e4d08d2855
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back.pysim: delay clock processes by one half period.
Makes it easier to see initial delta cycles.
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2018-12-14 05:17:43 +00:00 |
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whitequark
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3bb7a87e0f
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back.pysim: implement "sync processes", like migen.sim generators.
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2018-12-14 05:13:58 +00:00 |
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whitequark
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d791b77cc8
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back.pysim: allow suspending processes until a tick in a domain.
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2018-12-14 04:33:06 +00:00 |
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whitequark
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3e59d857e1
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back.pysim: use bare ints for signal values (-5% runtime).
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2018-12-14 03:05:57 +00:00 |
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whitequark
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b09f4b10ee
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back.pysim: collect handlers before running (-5% runtime).
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2018-12-13 18:34:44 +00:00 |
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whitequark
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a7ebc02bdd
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back.pysim: allow multiple registered handlers per signal.
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2018-12-13 18:28:11 +00:00 |
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whitequark
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6a4004ef8d
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back.pysim: fix handling of process termination.
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2018-12-13 18:17:58 +00:00 |
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whitequark
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fb27c2520b
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back.pysim: new simulator backend (WIP).
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2018-12-13 18:02:46 +00:00 |
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whitequark
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71f1f717c4
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fhdl.cd: rename ClockDomain signals together with domain.
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2018-12-13 15:24:55 +00:00 |
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whitequark
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07c818e077
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fhdl.ir: move Fragment prepare logic from back.rtlil.
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2018-12-13 14:34:07 +00:00 |
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whitequark
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ac498414ab
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back.verilog: remove debug code.
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2018-12-13 13:42:54 +00:00 |
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whitequark
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90f1503c91
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fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
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2018-12-13 13:12:31 +00:00 |
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whitequark
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6251c95d4e
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compat.genlib.fsm: import/wrap Migen code.
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2018-12-13 12:41:19 +00:00 |
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whitequark
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9661e897e6
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fhdl.ir: a subfragment's input that we don't drive is also our input.
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2018-12-13 11:50:56 +00:00 |
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whitequark
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bb04c9e0da
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fhdl, back: trace and emit source locations of values.
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2018-12-13 11:44:06 +00:00 |
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whitequark
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859c2dbcf0
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back.rtlil: never give subfragment cells names starting with $.
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2018-12-13 11:30:16 +00:00 |
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whitequark
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b150f1915d
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fhdl.ir: don't crash propagataing ports in empty fragments.
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2018-12-13 11:25:49 +00:00 |
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whitequark
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72257b6935
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fhdl.ir: implement clock domain propagation.
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2018-12-13 11:01:03 +00:00 |
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whitequark
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fde2471963
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fhdl.ir: remove iter_domains().
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2018-12-13 10:18:57 +00:00 |
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whitequark
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f4340c19bb
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fhdl: cd_name→domain.
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2018-12-13 10:15:01 +00:00 |
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whitequark
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c5087edfa5
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fhdl.cd: add tests.
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2018-12-13 09:19:16 +00:00 |
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whitequark
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9bee90f1bd
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fhdl.xfrm: implement DomainRenamer.
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2018-12-13 08:57:14 +00:00 |
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whitequark
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8963ab5d9f
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fhdl.xfrm: add test for ControlInserter with subfragments.
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2018-12-13 08:45:10 +00:00 |
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whitequark
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19aa404628
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fhdl.xfrm: add tests for ResetInserter, CEInserter.
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2018-12-13 08:39:02 +00:00 |
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whitequark
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b1a89ef5fd
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fhdl.ir: add tests for port propagation.
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2018-12-13 08:09:39 +00:00 |
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whitequark
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a797e27573
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fhdl.dsl: add tests for lowering. 99% branch coverage.
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2018-12-13 07:33:59 +00:00 |
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whitequark
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d2e2d00e45
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fhdl.cd: rename ClockDomain.{reset→rst}.
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2018-12-13 07:27:27 +00:00 |
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whitequark
|
e0a81edf4d
|
fhdl.dsl: add tests for submodules.
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2018-12-13 07:24:28 +00:00 |
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whitequark
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932f1912a2
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fhdl.dsl: use less error-prone Switch/Case two-level syntax.
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2018-12-13 07:11:06 +00:00 |
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whitequark
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f70ae3bac5
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fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
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2018-12-13 06:06:51 +00:00 |
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whitequark
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5b8708017e
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fhdl.ast: fix Switch._?hs_signals() for switch without statements.
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2018-12-13 05:00:44 +00:00 |
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whitequark
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4e32f6b8de
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back.verilog: detect undriven public wires using Yosys.
This should never happen, and is certainly a logic bug in nMigen.
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2018-12-13 04:59:48 +00:00 |
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whitequark
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27d3dfc453
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back.rtlil: fix swapped operands in sync assign.
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2018-12-13 04:34:22 +00:00 |
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whitequark
|
6c7f98e964
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back.rtlil: explain logic for CD reset insertion.
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2018-12-13 03:51:00 +00:00 |
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whitequark
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2c67a620ee
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back.rtlil: explicitly set the top module.
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2018-12-13 03:50:04 +00:00 |
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whitequark
|
4df5c5de65
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fhdl.ir: explain how port enumeration works.
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2018-12-13 03:31:13 +00:00 |
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whitequark
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f86ec1e7ef
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back.rtlil: explain how RTLIL conversion works.
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2018-12-13 03:22:01 +00:00 |
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whitequark
|
bfd0011aee
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fhdl.ir: make sure clocks and resets of used CDs appear as inputs.
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2018-12-13 02:43:22 +00:00 |
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whitequark
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a17a9e355d
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back.rtlil: give clocks and resets nicer names.
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2018-12-13 02:43:02 +00:00 |
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whitequark
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22c76e5f90
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compat.fhdl.module: implement finalization.
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2018-12-13 02:36:15 +00:00 |
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whitequark
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b42620e490
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back.rtlil: match shape of $mux ports A/B/Y.
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2018-12-13 02:35:46 +00:00 |
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whitequark
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17767642be
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tracer: add support for Python 3.7.
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2018-12-13 02:20:00 +00:00 |
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whitequark
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f0f4c0ce61
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fhdl.ast: bits_sign→shape.
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2018-12-13 02:06:58 +00:00 |
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whitequark
|
dc486ad8b9
|
fhdl.ast: add tests for most logic.
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2018-12-13 02:06:55 +00:00 |
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whitequark
|
b4dab74b2e
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compat.fhdl.{module,structure}: import/wrap Migen code (WIP).
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2018-12-12 15:47:34 +00:00 |
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whitequark
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356852a570
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compat.fhdl.bitcontainer: import/wrap Migen code.
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2018-12-12 15:22:34 +00:00 |
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whitequark
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1d4d00aac6
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fhdl.ast.Signal: implement .like().
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2018-12-12 14:43:19 +00:00 |
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whitequark
|
ad9b45adcd
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fhdl.ir: fix port threading code.
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2018-12-12 13:00:50 +00:00 |
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whitequark
|
0fac1f8d0f
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fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
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2018-12-12 12:38:24 +00:00 |
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whitequark
|
00f0b950f6
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fhdl.ast.Signal: fix typo.
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2018-12-12 12:37:30 +00:00 |
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whitequark
|
aab01d9e59
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fhdl.ast.Signal: implement attrs field.
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2018-12-12 11:30:40 +00:00 |
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whitequark
|
c05c189ece
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genlib.cdc.MultiReg: self.regs should be a private field.
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2018-12-12 10:52:32 +00:00 |
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whitequark
|
4eadc1629a
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fhdl.ast.Signal: implement width derivation from min/max.
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2018-12-12 10:43:09 +00:00 |
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whitequark
|
bc60631d68
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genlib.cdc.MultiReg: pull in from Migen.
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2018-12-12 10:12:35 +00:00 |
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whitequark
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263d577323
|
fhdl.ast.Signal: implement reset_less signals.
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2018-12-12 10:11:16 +00:00 |
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whitequark
|
1d46ffb591
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fhdl.ast.Signal: assign an internal name if tracer fails.
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2018-12-12 10:08:56 +00:00 |
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whitequark
|
6d5878a0ee
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fhdl.dsl: allow f.sync["dom"] as a synonym of f.sync.dom.
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2018-12-12 10:00:00 +00:00 |
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whitequark
|
851ed06769
|
ClockDomain.{rst→reset}, for consistency with ResetInserter.
nmigen.compat.ClockDomain would alias this, for Migen compatibility.
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2018-12-12 09:49:02 +00:00 |
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whitequark
|
4d3258013d
|
Initial commit.
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2018-12-12 03:18:44 +00:00 |
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