whitequark
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fa2af27bb0
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hdl.mem: ensure transparent read port model has correct latency.
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2018-12-21 13:01:08 +00:00 |
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whitequark
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af7db882c0
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hdl.mem: use different naming for array signals.
It looks like [] is confusing gtkwave somehow.
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2018-12-21 12:26:49 +00:00 |
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whitequark
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e58d9ec74d
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hdl.mem: add simulation model for memory.
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2018-12-21 11:54:32 +00:00 |
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whitequark
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c49211c76a
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hdl.mem: add tests for all error conditions.
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2018-12-21 06:07:16 +00:00 |
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whitequark
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a061bfaa6c
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hdl.mem: tie rdport.en high for asynchronous or transparent ports.
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2018-12-21 04:22:16 +00:00 |
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whitequark
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6d9a6b5d84
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hdl.mem: implement memories.
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2018-12-21 01:53:32 +00:00 |
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