amaranth/amaranth/back
2025-08-18 17:46:28 +02:00
..
__init__.py Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
cxxrtl.py backends: s/ilang/rtlil as a result of https://github.com/YosysHQ/yosys/pull/4704 2025-08-18 17:46:28 +02:00
rtlil.py back.rtlil: set read port init to all-x. 2024-05-09 02:38:53 +00:00
verilog.py backends: s/ilang/rtlil as a result of https://github.com/YosysHQ/yosys/pull/4704 2025-08-18 17:46:28 +02:00