5dd1223cf8
This change completes commit 9dc0617e and makes all the tests pass. It corresponds with the ongoing langauge reference documentation effort. Fixes #781.
80 lines
2.7 KiB
Python
80 lines
2.7 KiB
Python
from amaranth.hdl._cd import *
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from .utils import *
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class ClockDomainTestCase(FHDLTestCase):
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def test_name(self):
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sync = ClockDomain()
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self.assertEqual(sync.name, "sync")
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self.assertEqual(sync.clk.name, "clk")
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self.assertEqual(sync.rst.name, "rst")
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self.assertEqual(sync.local, False)
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pix = ClockDomain()
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self.assertEqual(pix.name, "pix")
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self.assertEqual(pix.clk.name, "pix_clk")
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self.assertEqual(pix.rst.name, "pix_rst")
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cd_pix = ClockDomain()
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self.assertEqual(cd_pix.name, "pix")
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dom = [ClockDomain("foo")][0]
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self.assertEqual(dom.name, "foo")
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with self.assertRaisesRegex(ValueError,
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r"^Clock domain name must be specified explicitly$"):
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ClockDomain()
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cd_reset = ClockDomain(local=True)
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self.assertEqual(cd_reset.local, True)
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def test_edge(self):
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sync = ClockDomain()
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self.assertEqual(sync.clk_edge, "pos")
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sync = ClockDomain(clk_edge="pos")
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self.assertEqual(sync.clk_edge, "pos")
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sync = ClockDomain(clk_edge="neg")
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self.assertEqual(sync.clk_edge, "neg")
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def test_edge_wrong(self):
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with self.assertRaisesRegex(ValueError,
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r"^Domain clock edge must be one of 'pos' or 'neg', not 'xxx'$"):
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ClockDomain("sync", clk_edge="xxx")
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def test_with_reset(self):
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pix = ClockDomain()
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self.assertIsNotNone(pix.clk)
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self.assertIsNotNone(pix.rst)
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self.assertFalse(pix.async_reset)
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def test_without_reset(self):
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pix = ClockDomain(reset_less=True)
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self.assertIsNotNone(pix.clk)
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self.assertIsNone(pix.rst)
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self.assertFalse(pix.async_reset)
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def test_async_reset(self):
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pix = ClockDomain(async_reset=True)
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self.assertIsNotNone(pix.clk)
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self.assertIsNotNone(pix.rst)
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self.assertTrue(pix.async_reset)
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def test_rename(self):
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sync = ClockDomain()
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self.assertEqual(sync.name, "sync")
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self.assertEqual(sync.clk.name, "clk")
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self.assertEqual(sync.rst.name, "rst")
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sync.rename("pix")
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self.assertEqual(sync.name, "pix")
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self.assertEqual(sync.clk.name, "pix_clk")
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self.assertEqual(sync.rst.name, "pix_rst")
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def test_rename_reset_less(self):
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sync = ClockDomain(reset_less=True)
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self.assertEqual(sync.name, "sync")
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self.assertEqual(sync.clk.name, "clk")
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sync.rename("pix")
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self.assertEqual(sync.name, "pix")
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self.assertEqual(sync.clk.name, "pix_clk")
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def test_wrong_name_comb(self):
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with self.assertRaisesRegex(ValueError,
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r"^Domain 'comb' may not be clocked$"):
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comb = ClockDomain()
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