whitequark fa2af27bb0 hdl.mem: ensure transparent read port model has correct latency.		2018-12-21 13:01:08 +00:00
..
__init__.py	fhdl.ast: add tests for most logic.	2018-12-13 02:06:55 +00:00
test_hdl_ast.py	hdl.ast: Cat.{operands→parts}	2018-12-18 19:15:50 +00:00
test_hdl_cd.py	hdl.mem: add tests for all error conditions.	2018-12-21 06:07:16 +00:00
test_hdl_dsl.py	hdl, back: add and use SignalSet/SignalDict.	2018-12-17 17:21:29 +00:00
test_hdl_ir.py	hdl.ir: correctly handle named output and inout ports.	2018-12-21 04:03:03 +00:00
test_hdl_mem.py	hdl.mem: add tests for all error conditions.	2018-12-21 06:07:16 +00:00
test_hdl_xfrm.py	hdl, back: add and use SignalSet/SignalDict.	2018-12-17 17:21:29 +00:00
test_sim.py	hdl.mem: ensure transparent read port model has correct latency.	2018-12-21 13:01:08 +00:00
tools.py	hdl.ast: implement Array and ArrayProxy.	2018-12-15 17:16:31 +00:00