whitequark 06faeee357 back.verilog: better error message if Yosys is not found. ... Fixes #17.		2019-01-13 08:10:23 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	Give the top level scope a name to fix VCD hierarchy.	2019-01-06 00:10:37 +00:00
rtlil.py	back.rtlil: translate empty slices correctly.	2019-01-02 18:14:29 +00:00
verilog.py	back.verilog: better error message if Yosys is not found.	2019-01-13 08:10:23 +00:00