b65e11f38f
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
128 lines
3.6 KiB
Python
128 lines
3.6 KiB
Python
from nmigen.hdl import *
|
|
from nmigen.asserts import *
|
|
from nmigen.sim import *
|
|
from nmigen.lib.coding import *
|
|
|
|
from .utils import *
|
|
|
|
|
|
class EncoderTestCase(FHDLTestCase):
|
|
def test_basic(self):
|
|
enc = Encoder(4)
|
|
def process():
|
|
self.assertEqual((yield enc.n), 1)
|
|
self.assertEqual((yield enc.o), 0)
|
|
|
|
yield enc.i.eq(0b0001)
|
|
yield Settle()
|
|
self.assertEqual((yield enc.n), 0)
|
|
self.assertEqual((yield enc.o), 0)
|
|
|
|
yield enc.i.eq(0b0100)
|
|
yield Settle()
|
|
self.assertEqual((yield enc.n), 0)
|
|
self.assertEqual((yield enc.o), 2)
|
|
|
|
yield enc.i.eq(0b0110)
|
|
yield Settle()
|
|
self.assertEqual((yield enc.n), 1)
|
|
self.assertEqual((yield enc.o), 0)
|
|
|
|
sim = Simulator(enc)
|
|
sim.add_process(process)
|
|
sim.run()
|
|
|
|
|
|
class PriorityEncoderTestCase(FHDLTestCase):
|
|
def test_basic(self):
|
|
enc = PriorityEncoder(4)
|
|
def process():
|
|
self.assertEqual((yield enc.n), 1)
|
|
self.assertEqual((yield enc.o), 0)
|
|
|
|
yield enc.i.eq(0b0001)
|
|
yield Settle()
|
|
self.assertEqual((yield enc.n), 0)
|
|
self.assertEqual((yield enc.o), 0)
|
|
|
|
yield enc.i.eq(0b0100)
|
|
yield Settle()
|
|
self.assertEqual((yield enc.n), 0)
|
|
self.assertEqual((yield enc.o), 2)
|
|
|
|
yield enc.i.eq(0b0110)
|
|
yield Settle()
|
|
self.assertEqual((yield enc.n), 0)
|
|
self.assertEqual((yield enc.o), 1)
|
|
|
|
sim = Simulator(enc)
|
|
sim.add_process(process)
|
|
sim.run()
|
|
|
|
|
|
class DecoderTestCase(FHDLTestCase):
|
|
def test_basic(self):
|
|
dec = Decoder(4)
|
|
def process():
|
|
self.assertEqual((yield dec.o), 0b0001)
|
|
|
|
yield dec.i.eq(1)
|
|
yield Settle()
|
|
self.assertEqual((yield dec.o), 0b0010)
|
|
|
|
yield dec.i.eq(3)
|
|
yield Settle()
|
|
self.assertEqual((yield dec.o), 0b1000)
|
|
|
|
yield dec.n.eq(1)
|
|
yield Settle()
|
|
self.assertEqual((yield dec.o), 0b0000)
|
|
|
|
sim = Simulator(dec)
|
|
sim.add_process(process)
|
|
sim.run()
|
|
|
|
|
|
class ReversibleSpec(Elaboratable):
|
|
def __init__(self, encoder_cls, decoder_cls, args):
|
|
self.encoder_cls = encoder_cls
|
|
self.decoder_cls = decoder_cls
|
|
self.coder_args = args
|
|
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
enc, dec = self.encoder_cls(*self.coder_args), self.decoder_cls(*self.coder_args)
|
|
m.submodules += enc, dec
|
|
m.d.comb += [
|
|
dec.i.eq(enc.o),
|
|
Assert(enc.i == dec.o)
|
|
]
|
|
return m
|
|
|
|
|
|
class HammingDistanceSpec(Elaboratable):
|
|
def __init__(self, distance, encoder_cls, args):
|
|
self.distance = distance
|
|
self.encoder_cls = encoder_cls
|
|
self.coder_args = args
|
|
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
enc1, enc2 = self.encoder_cls(*self.coder_args), self.encoder_cls(*self.coder_args)
|
|
m.submodules += enc1, enc2
|
|
m.d.comb += [
|
|
Assume(enc1.i + 1 == enc2.i),
|
|
Assert(sum(enc1.o ^ enc2.o) == self.distance)
|
|
]
|
|
return m
|
|
|
|
|
|
class GrayCoderTestCase(FHDLTestCase):
|
|
def test_reversible(self):
|
|
spec = ReversibleSpec(encoder_cls=GrayEncoder, decoder_cls=GrayDecoder, args=(16,))
|
|
self.assertFormal(spec, mode="prove")
|
|
|
|
def test_distance(self):
|
|
spec = HammingDistanceSpec(distance=1, encoder_cls=GrayEncoder, args=(16,))
|
|
self.assertFormal(spec, mode="prove")
|