50 lines
1.3 KiB
Verilog
50 lines
1.3 KiB
Verilog
(* generator = "nMigen" *)
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module top(clk, rst, en, ovf);
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(* src = "<nmigen-root>/nmigen/hdl/ir.py:526" *)
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input clk;
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(* src = "<nmigen-root>/nmigen/hdl/ir.py:526" *)
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input rst;
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(* src = "up_counter.py:26" *)
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input en;
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(* src = "up_counter.py:27" *)
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output ovf;
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(* src = "up_counter.py:30" *)
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reg [15:0] count = 16'h0000;
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(* src = "up_counter.py:30" *)
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reg [15:0] \count$next ;
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(* src = "up_counter.py:35" *)
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wire \$1 ;
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(* src = "up_counter.py:41" *)
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wire [16:0] \$3 ;
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(* src = "up_counter.py:41" *)
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wire [16:0] \$4 ;
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assign \$1 = count == (* src = "up_counter.py:35" *) 5'h19;
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assign \$4 = count + (* src = "up_counter.py:41" *) 1'h1;
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always @(posedge clk)
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count <= \count$next ;
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always @* begin
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\count$next = count;
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(* src = "up_counter.py:37" *)
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casez (en)
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/* src = "up_counter.py:37" */
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1'h1:
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(* src = "up_counter.py:38" *)
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casez (ovf)
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/* src = "up_counter.py:38" */
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1'h1:
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\count$next = 16'h0000;
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/* src = "up_counter.py:40" */
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default:
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\count$next = \$3 [15:0];
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endcase
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endcase
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(* src = "<nmigen-root>/nmigen/hdl/xfrm.py:518" *)
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casez (rst)
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1'h1:
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\count$next = 16'h0000;
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endcase
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end
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assign \$3 = \$4 ;
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assign ovf = \$1 ;
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endmodule
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