323 lines
12 KiB
Python
323 lines
12 KiB
Python
import operator
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from collections import OrderedDict
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from .. import tracer
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from .ast import *
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from .ir import Elaboratable, Instance
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__all__ = ["Memory", "ReadPort", "WritePort", "DummyPort"]
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class Memory:
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"""A word addressable storage.
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Parameters
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----------
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width : int
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Access granularity. Each storage element of this memory is ``width`` bits in size.
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depth : int
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Word count. This memory contains ``depth`` storage elements.
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init : list of int
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Initial values. At power on, each storage element in this memory is initialized to
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the corresponding element of ``init``, if any, or to zero otherwise.
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Uninitialized memories are not currently supported.
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name : str
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Name hint for this memory. If ``None`` (default) the name is inferred from the variable
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name this ``Signal`` is assigned to.
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attrs : dict
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Dictionary of synthesis attributes.
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Attributes
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----------
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width : int
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depth : int
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init : list of int
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attrs : dict
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"""
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def __init__(self, *, width, depth, init=None, name=None, attrs=None, simulate=True):
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if not isinstance(width, int) or width < 0:
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raise TypeError("Memory width must be a non-negative integer, not {!r}"
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.format(width))
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if not isinstance(depth, int) or depth < 0:
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raise TypeError("Memory depth must be a non-negative integer, not {!r}"
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.format(depth))
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self.name = name or tracer.get_var_name(depth=2, default="$memory")
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self.src_loc = tracer.get_src_loc()
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self.width = width
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self.depth = depth
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self.attrs = OrderedDict(() if attrs is None else attrs)
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# Array of signals for simulation.
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self._array = Array()
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if simulate:
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for addr in range(self.depth):
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self._array.append(Signal(self.width, name="{}({})"
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.format(name or "memory", addr)))
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self.init = init
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@property
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def init(self):
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return self._init
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@init.setter
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def init(self, new_init):
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self._init = [] if new_init is None else list(new_init)
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if len(self.init) > self.depth:
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raise ValueError("Memory initialization value count exceed memory depth ({} > {})"
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.format(len(self.init), self.depth))
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try:
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for addr in range(len(self._array)):
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if addr < len(self._init):
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self._array[addr].reset = operator.index(self._init[addr])
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else:
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self._array[addr].reset = 0
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except TypeError as e:
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raise TypeError("Memory initialization value at address {:x}: {}"
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.format(addr, e)) from None
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def read_port(self, *, src_loc_at=0, **kwargs):
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"""Get a read port.
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See :class:`ReadPort` for details.
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Arguments
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---------
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domain : str
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transparent : bool
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Returns
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-------
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An instance of :class:`ReadPort` associated with this memory.
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"""
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return ReadPort(self, src_loc_at=1 + src_loc_at, **kwargs)
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def write_port(self, *, src_loc_at=0, **kwargs):
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"""Get a write port.
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See :class:`WritePort` for details.
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Arguments
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---------
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domain : str
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granularity : int
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Returns
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-------
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An instance of :class:`WritePort` associated with this memory.
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"""
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return WritePort(self, src_loc_at=1 + src_loc_at, **kwargs)
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def __getitem__(self, index):
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"""Simulation only."""
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return self._array[index]
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class ReadPort(Elaboratable):
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"""A memory read port.
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Parameters
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----------
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memory : :class:`Memory`
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Memory associated with the port.
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domain : str
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Clock domain. Defaults to ``"sync"``. If set to ``"comb"``, the port is asynchronous.
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Otherwise, the read data becomes available on the next clock cycle.
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transparent : bool
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Port transparency. If set (default), a read at an address that is also being written to in
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the same clock cycle will output the new value. Otherwise, the old value will be output
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first. This behavior only applies to ports in the same domain.
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Attributes
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----------
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memory : :class:`Memory`
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domain : str
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transparent : bool
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addr : Signal(range(memory.depth)), in
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Read address.
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data : Signal(memory.width), out
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Read data.
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en : Signal or Const, in
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Read enable. If asserted, ``data`` is updated with the word stored at ``addr``. Note that
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transparent ports cannot assign ``en`` (which is hardwired to 1 instead), as doing so is
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currently not supported by Yosys.
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Exceptions
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----------
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Raises :exn:`ValueError` if the read port is simultaneously asynchronous and non-transparent.
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"""
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def __init__(self, memory, *, domain="sync", transparent=True, src_loc_at=0):
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if domain == "comb" and not transparent:
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raise ValueError("Read port cannot be simultaneously asynchronous and non-transparent")
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self.memory = memory
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self.domain = domain
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self.transparent = transparent
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self.addr = Signal(range(memory.depth),
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name="{}_r_addr".format(memory.name), src_loc_at=1 + src_loc_at)
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self.data = Signal(memory.width,
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name="{}_r_data".format(memory.name), src_loc_at=1 + src_loc_at)
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if self.domain != "comb" and not transparent:
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self.en = Signal(name="{}_r_en".format(memory.name), reset=1,
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src_loc_at=1 + src_loc_at)
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else:
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self.en = Const(1)
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def elaborate(self, platform):
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f = Instance("$memrd",
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p_MEMID=self.memory,
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p_ABITS=self.addr.width,
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p_WIDTH=self.data.width,
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p_CLK_ENABLE=self.domain != "comb",
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p_CLK_POLARITY=1,
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p_TRANSPARENT=self.transparent,
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i_CLK=ClockSignal(self.domain) if self.domain != "comb" else Const(0),
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i_EN=self.en,
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i_ADDR=self.addr,
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o_DATA=self.data,
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)
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if self.domain == "comb":
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# Asynchronous port
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f.add_statements(self.data.eq(self.memory._array[self.addr]))
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f.add_driver(self.data)
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elif not self.transparent:
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# Synchronous, read-before-write port
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f.add_statements(
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Switch(self.en, {
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1: self.data.eq(self.memory._array[self.addr])
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})
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)
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f.add_driver(self.data, self.domain)
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else:
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# Synchronous, write-through port
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# This model is a bit unconventional. We model transparent ports as asynchronous ports
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# that are latched when the clock is high. This isn't exactly correct, but it is very
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# close to the correct behavior of a transparent port, and the difference should only
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# be observable in pathological cases of clock gating. A register is injected to
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# the address input to achieve the correct address-to-data latency. Also, the reset
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# value of the data output is forcibly set to the 0th initial value, if any--note that
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# many FPGAs do not guarantee this behavior!
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if len(self.memory.init) > 0:
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self.data.reset = operator.index(self.memory.init[0])
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latch_addr = Signal.like(self.addr)
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f.add_statements(
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latch_addr.eq(self.addr),
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Switch(ClockSignal(self.domain), {
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0: self.data.eq(self.data),
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1: self.data.eq(self.memory._array[latch_addr]),
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}),
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)
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f.add_driver(latch_addr, self.domain)
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f.add_driver(self.data)
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return f
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class WritePort(Elaboratable):
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"""A memory write port.
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Parameters
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----------
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memory : :class:`Memory`
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Memory associated with the port.
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domain : str
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Clock domain. Defaults to ``"sync"``. Writes have a latency of 1 clock cycle.
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granularity : int
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Port granularity. Defaults to ``memory.width``. Write data is split evenly in
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``memory.width // granularity`` chunks, which can be updated independently.
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Attributes
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----------
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memory : :class:`Memory`
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domain : str
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granularity : int
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addr : Signal(range(memory.depth)), in
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Write address.
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data : Signal(memory.width), in
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Write data.
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en : Signal(memory.width // granularity), in
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Write enable. Each bit selects a non-overlapping chunk of ``granularity`` bits on the
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``data`` signal, which is written to memory at ``addr``. Unselected chunks are ignored.
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Exceptions
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----------
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Raises :exn:`ValueError` if the write port granularity is greater than memory width, or does not
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divide memory width evenly.
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"""
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def __init__(self, memory, *, domain="sync", granularity=None, src_loc_at=0):
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if granularity is None:
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granularity = memory.width
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if not isinstance(granularity, int) or granularity < 0:
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raise TypeError("Write port granularity must be a non-negative integer, not {!r}"
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.format(granularity))
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if granularity > memory.width:
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raise ValueError("Write port granularity must not be greater than memory width "
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"({} > {})"
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.format(granularity, memory.width))
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if memory.width // granularity * granularity != memory.width:
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raise ValueError("Write port granularity must divide memory width evenly")
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self.memory = memory
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self.domain = domain
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self.granularity = granularity
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self.addr = Signal(range(memory.depth),
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name="{}_w_addr".format(memory.name), src_loc_at=1 + src_loc_at)
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self.data = Signal(memory.width,
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name="{}_w_data".format(memory.name), src_loc_at=1 + src_loc_at)
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self.en = Signal(memory.width // granularity,
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name="{}_w_en".format(memory.name), src_loc_at=1 + src_loc_at)
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def elaborate(self, platform):
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f = Instance("$memwr",
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p_MEMID=self.memory,
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p_ABITS=self.addr.width,
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p_WIDTH=self.data.width,
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p_CLK_ENABLE=1,
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p_CLK_POLARITY=1,
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p_PRIORITY=0,
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i_CLK=ClockSignal(self.domain),
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i_EN=Cat(Repl(en_bit, self.granularity) for en_bit in self.en),
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i_ADDR=self.addr,
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i_DATA=self.data,
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)
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if len(self.en) > 1:
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for index, en_bit in enumerate(self.en):
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offset = index * self.granularity
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bits = slice(offset, offset + self.granularity)
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write_data = self.memory._array[self.addr][bits].eq(self.data[bits])
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f.add_statements(Switch(en_bit, { 1: write_data }))
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else:
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write_data = self.memory._array[self.addr].eq(self.data)
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f.add_statements(Switch(self.en, { 1: write_data }))
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for signal in self.memory._array:
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f.add_driver(signal, self.domain)
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return f
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class DummyPort:
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"""Dummy memory port.
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This port can be used in place of either a read or a write port for testing and verification.
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It does not include any read/write port specific attributes, i.e. none besides ``"domain"``;
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any such attributes may be set manually.
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"""
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def __init__(self, *, data_width, addr_width, domain="sync", name=None, granularity=None):
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self.domain = domain
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if granularity is None:
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granularity = data_width
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if name is None:
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name = tracer.get_var_name(depth=2, default="dummy")
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self.addr = Signal(addr_width,
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name="{}_addr".format(name), src_loc_at=1)
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self.data = Signal(data_width,
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name="{}_data".format(name), src_loc_at=1)
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self.en = Signal(data_width // granularity,
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name="{}_en".format(name), src_loc_at=1)
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