b65e11f38f
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
97 lines
3.1 KiB
Python
97 lines
3.1 KiB
Python
# nmigen: UnusedElaboratable=no
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import unittest
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from nmigen.hdl import *
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from nmigen.asserts import *
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from nmigen.sim import *
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from nmigen.lib.scheduler import *
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from .utils import *
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class RoundRobinTestCase(unittest.TestCase):
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def test_count(self):
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dut = RoundRobin(count=32)
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self.assertEqual(dut.count, 32)
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self.assertEqual(len(dut.requests), 32)
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self.assertEqual(len(dut.grant), 5)
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def test_wrong_count(self):
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with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not 'foo'"):
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dut = RoundRobin(count="foo")
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with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not -1"):
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dut = RoundRobin(count=-1)
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class RoundRobinSimulationTestCase(unittest.TestCase):
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def test_count_one(self):
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dut = RoundRobin(count=1)
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sim = Simulator(dut)
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def process():
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yield dut.requests.eq(0)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertFalse((yield dut.valid))
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yield dut.requests.eq(1)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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sim.add_sync_process(process)
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sim.add_clock(1e-6)
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with sim.write_vcd("test.vcd"):
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sim.run()
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def test_transitions(self):
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dut = RoundRobin(count=3)
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sim = Simulator(dut)
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def process():
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yield dut.requests.eq(0b111)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 1)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b110)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 2)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b010)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 1)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b011)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b001)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b101)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 2)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b100)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 2)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b000)
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yield; yield Delay(1e-8)
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self.assertFalse((yield dut.valid))
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yield dut.requests.eq(0b001)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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sim.add_sync_process(process)
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sim.add_clock(1e-6)
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with sim.write_vcd("test.vcd"):
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sim.run()
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