whitequark 10e56c75fb back.verilog: run proc_prune for much cleaner output. ... This is a very new Yosys feature, and will require a Yosys build newer than YosysHQ/yosys@44bcb7a1.		2019-07-09 19:28:09 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: create unique ResetSynchronizer internal domains.	2019-06-28 08:34:43 +00:00
rtlil.py	hdl.{ast,dsl},back.rtlil: track source locations for switch cases.	2019-07-09 19:26:47 +00:00
verilog.py	back.verilog: run proc_prune for much cleaner output.	2019-07-09 19:28:09 +00:00