whitequark 00c5209a47 hdl.{ast,dsl},back.rtlil: track source locations for switch cases. ... This is a very new Yosys feature, and will require a Yosys build newer than YosysHQ/yosys@93bc5aff.		2019-07-09 19:26:47 +00:00
..
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
ast.py	hdl.{ast,dsl},back.rtlil: track source locations for switch cases.	2019-07-09 19:26:47 +00:00
cd.py	hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.	2019-07-08 10:26:49 +00:00
dsl.py	hdl.{ast,dsl},back.rtlil: track source locations for switch cases.	2019-07-09 19:26:47 +00:00
ir.py	hdl.ir, back.rtlil: allow specifying attributes on instances.	2019-06-28 04:14:38 +00:00
mem.py	hdl.{dsl,mem,xfrm}: inject appropriate source locations.	2019-07-08 09:58:12 +00:00
rec.py	hdl.rec: respect modifications to signals in Record.like().	2019-07-08 10:59:15 +00:00
xfrm.py	hdl.{ast,dsl},back.rtlil: track source locations for switch cases.	2019-07-09 19:26:47 +00:00