580 lines
22 KiB
Python
580 lines
22 KiB
Python
"""First-in first-out queues."""
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import warnings
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from .. import *
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from ..asserts import *
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from ..utils import ceil_log2
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from .coding import GrayEncoder, GrayDecoder
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from .cdc import FFSynchronizer, AsyncFFSynchronizer
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__all__ = ["FIFOInterface", "SyncFIFO", "SyncFIFOBuffered", "AsyncFIFO", "AsyncFIFOBuffered"]
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class FIFOInterface:
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_doc_template = """
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{description}
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Parameters
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----------
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width : int
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Bit width of data entries.
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depth : int
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Depth of the queue. If zero, the FIFO cannot be read from or written to.
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{parameters}
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Attributes
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----------
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{attributes}
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w_data : Signal(width), in
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Input data.
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w_rdy : Signal(1), out
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Asserted if there is space in the queue, i.e. ``w_en`` can be asserted to write
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a new entry.
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w_en : Signal(1), in
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Write strobe. Latches ``w_data`` into the queue. Does nothing if ``w_rdy`` is not asserted.
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w_level : Signal(range(depth + 1)), out
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Number of unread entries.
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{w_attributes}
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r_data : Signal(width), out
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Output data. {r_data_valid}
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r_rdy : Signal(1), out
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Asserted if there is an entry in the queue, i.e. ``r_en`` can be asserted to read
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an existing entry.
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r_en : Signal(1), in
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Read strobe. Makes the next entry (if any) available on ``r_data`` at the next cycle.
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Does nothing if ``r_rdy`` is not asserted.
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r_level : Signal(range(depth + 1)), out
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Number of unread entries.
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{r_attributes}
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"""
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__doc__ = _doc_template.format(description="""
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Data written to the input interface (``w_data``, ``w_rdy``, ``w_en``) is buffered and can be
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read at the output interface (``r_data``, ``r_rdy``, ``r_en``). The data entry written first
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to the input also appears first on the output.
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""",
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parameters="",
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r_data_valid="The conditions in which ``r_data`` is valid depends on the type of the queue.",
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attributes="",
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w_attributes="",
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r_attributes="")
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def __init__(self, *, width, depth):
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if not isinstance(width, int) or width < 0:
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raise TypeError("FIFO width must be a non-negative integer, not {!r}"
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.format(width))
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if not isinstance(depth, int) or depth < 0:
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raise TypeError("FIFO depth must be a non-negative integer, not {!r}"
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.format(depth))
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self.width = width
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self.depth = depth
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self.w_data = Signal(width, reset_less=True)
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self.w_rdy = Signal() # writable; not full
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self.w_en = Signal()
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self.w_level = Signal(range(depth + 1))
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self.r_data = Signal(width, reset_less=True)
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self.r_rdy = Signal() # readable; not empty
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self.r_en = Signal()
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self.r_level = Signal(range(depth + 1))
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def _incr(signal, modulo):
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if modulo == 2 ** len(signal):
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return signal + 1
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else:
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return Mux(signal == modulo - 1, 0, signal + 1)
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class SyncFIFO(Elaboratable, FIFOInterface):
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__doc__ = FIFOInterface._doc_template.format(
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description="""
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Synchronous first in, first out queue.
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Read and write interfaces are accessed from the same clock domain. If different clock domains
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are needed, use :class:`AsyncFIFO`.
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""".strip(),
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parameters="",
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r_data_valid="Valid if ``r_rdy`` is asserted.",
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attributes="""
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level : Signal(range(depth + 1)), out
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Number of unread entries. This level is the same between read and write for synchronous FIFOs.
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""".strip(),
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r_attributes="",
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w_attributes="")
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def __init__(self, *, width, depth):
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super().__init__(width=width, depth=depth)
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self.level = Signal(range(depth + 1))
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def elaborate(self, platform):
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m = Module()
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if self.depth == 0:
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m.d.comb += [
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self.w_rdy.eq(0),
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self.r_rdy.eq(0),
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]
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return m
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m.d.comb += [
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self.w_rdy.eq(self.level != self.depth),
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self.r_rdy.eq(self.level != 0),
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self.w_level.eq(self.level),
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self.r_level.eq(self.level),
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]
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do_read = self.r_rdy & self.r_en
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do_write = self.w_rdy & self.w_en
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storage = m.submodules.storage = Memory(width=self.width, depth=self.depth)
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w_port = storage.write_port()
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r_port = storage.read_port(domain="comb")
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produce = Signal(range(self.depth))
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consume = Signal(range(self.depth))
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m.d.comb += [
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w_port.addr.eq(produce),
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w_port.data.eq(self.w_data),
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w_port.en.eq(self.w_en & self.w_rdy),
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]
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with m.If(do_write):
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m.d.sync += produce.eq(_incr(produce, self.depth))
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m.d.comb += [
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r_port.addr.eq(consume),
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self.r_data.eq(r_port.data),
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]
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with m.If(do_read):
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m.d.sync += consume.eq(_incr(consume, self.depth))
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with m.If(do_write & ~do_read):
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m.d.sync += self.level.eq(self.level + 1)
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with m.If(do_read & ~do_write):
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m.d.sync += self.level.eq(self.level - 1)
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if platform == "formal":
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# TODO: move this logic to SymbiYosys
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with m.If(Initial()):
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m.d.comb += [
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Assume(produce < self.depth),
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Assume(consume < self.depth),
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]
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with m.If(produce == consume):
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m.d.comb += Assume((self.level == 0) | (self.level == self.depth))
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with m.If(produce > consume):
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m.d.comb += Assume(self.level == (produce - consume))
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with m.If(produce < consume):
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m.d.comb += Assume(self.level == (self.depth + produce - consume))
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with m.Else():
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m.d.comb += [
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Assert(produce < self.depth),
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Assert(consume < self.depth),
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]
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with m.If(produce == consume):
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m.d.comb += Assert((self.level == 0) | (self.level == self.depth))
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with m.If(produce > consume):
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m.d.comb += Assert(self.level == (produce - consume))
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with m.If(produce < consume):
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m.d.comb += Assert(self.level == (self.depth + produce - consume))
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return m
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class SyncFIFOBuffered(Elaboratable, FIFOInterface):
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__doc__ = FIFOInterface._doc_template.format(
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description="""
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Buffered synchronous first in, first out queue.
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This queue's interface is identical to :class:`SyncFIFO`, but it
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does not use asynchronous memory reads, which are incompatible with FPGA block RAMs.
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In exchange, the latency between an entry being written to an empty queue and that entry
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becoming available on the output is increased by one cycle compared to :class:`SyncFIFO`.
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""".strip(),
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parameters="",
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attributes="""
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level : Signal(range(depth + 1)), out
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Number of unread entries. This level is the same between read and write for synchronous FIFOs.
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""".strip(),
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r_data_valid="Valid if ``r_rdy`` is asserted.",
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r_attributes="",
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w_attributes="")
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def __init__(self, *, width, depth):
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super().__init__(width=width, depth=depth)
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self.level = Signal(range(depth + 1))
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def elaborate(self, platform):
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m = Module()
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if self.depth == 0:
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m.d.comb += [
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self.w_rdy.eq(0),
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self.r_rdy.eq(0),
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]
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return m
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do_write = self.w_rdy & self.w_en
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do_read = self.r_rdy & self.r_en
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m.d.comb += [
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self.w_level.eq(self.level),
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self.r_level.eq(self.level),
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]
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if self.depth == 1:
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# Special case: a single register. Note that, by construction, this will
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# only be able to push a value every other cycle (alternating between
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# full and empty).
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m.d.comb += [
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self.w_rdy.eq(self.level == 0),
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self.r_rdy.eq(self.level == 1),
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]
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with m.If(do_write):
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m.d.sync += [
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self.r_data.eq(self.w_data),
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self.level.eq(1),
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]
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with m.If(do_read):
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m.d.sync += [
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self.level.eq(0),
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]
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return m
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inner_depth = self.depth - 1
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inner_level = Signal(range(inner_depth + 1))
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inner_r_rdy = Signal()
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m.d.comb += [
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self.w_rdy.eq(inner_level != inner_depth),
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inner_r_rdy.eq(inner_level != 0),
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]
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do_inner_read = inner_r_rdy & (~self.r_rdy | self.r_en)
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storage = m.submodules.storage = Memory(width=self.width, depth=inner_depth)
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w_port = storage.write_port()
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r_port = storage.read_port(domain="sync", transparent=False)
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produce = Signal(range(inner_depth))
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consume = Signal(range(inner_depth))
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m.d.comb += [
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w_port.addr.eq(produce),
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w_port.data.eq(self.w_data),
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w_port.en.eq(do_write),
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]
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with m.If(do_write):
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m.d.sync += produce.eq(_incr(produce, inner_depth))
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m.d.comb += [
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r_port.addr.eq(consume),
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self.r_data.eq(r_port.data),
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r_port.en.eq(do_inner_read)
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]
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with m.If(do_inner_read):
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m.d.sync += consume.eq(_incr(consume, inner_depth))
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with m.If(do_write & ~do_inner_read):
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m.d.sync += inner_level.eq(inner_level + 1)
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with m.If(do_inner_read & ~do_write):
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m.d.sync += inner_level.eq(inner_level - 1)
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with m.If(do_inner_read):
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m.d.sync += self.r_rdy.eq(1)
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with m.Elif(self.r_en):
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m.d.sync += self.r_rdy.eq(0)
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m.d.comb += [
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self.level.eq(inner_level + self.r_rdy),
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]
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if platform == "formal":
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# TODO: move this logic to SymbiYosys
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with m.If(Initial()):
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m.d.comb += [
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Assume(produce < inner_depth),
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Assume(consume < inner_depth),
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]
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with m.If(produce == consume):
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m.d.comb += Assume((inner_level == 0) | (inner_level == inner_depth))
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with m.If(produce > consume):
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m.d.comb += Assume(inner_level == (produce - consume))
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with m.If(produce < consume):
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m.d.comb += Assume(inner_level == (inner_depth + produce - consume))
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with m.Else():
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m.d.comb += [
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Assert(produce < inner_depth),
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Assert(consume < inner_depth),
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]
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with m.If(produce == consume):
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m.d.comb += Assert((inner_level == 0) | (inner_level == inner_depth))
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with m.If(produce > consume):
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m.d.comb += Assert(inner_level == (produce - consume))
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with m.If(produce < consume):
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m.d.comb += Assert(inner_level == (inner_depth + produce - consume))
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return m
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class AsyncFIFO(Elaboratable, FIFOInterface):
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__doc__ = FIFOInterface._doc_template.format(
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description="""
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Asynchronous first in, first out queue.
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Read and write interfaces are accessed from different clock domains, which can be set when
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constructing the FIFO.
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:class:`AsyncFIFO` can be reset from the write clock domain. When the write domain reset is
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asserted, the FIFO becomes empty. When the read domain is reset, data remains in the FIFO - the
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read domain logic should correctly handle this case.
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:class:`AsyncFIFO` only supports power of 2 depths. Unless ``exact_depth`` is specified,
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the ``depth`` parameter is rounded up to the next power of 2.
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""".strip(),
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parameters="""
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r_domain : str
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Read clock domain.
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w_domain : str
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Write clock domain.
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""".strip(),
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attributes="",
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r_data_valid="Valid if ``r_rdy`` is asserted.",
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r_attributes="""
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r_rst : Signal(1), out
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Asserted, for at least one read-domain clock cycle, after the FIFO has been reset by
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the write-domain reset.
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""".strip(),
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w_attributes="")
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def __init__(self, *, width, depth, r_domain="read", w_domain="write", exact_depth=False):
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if depth != 0:
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depth_bits = ceil_log2(depth)
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if exact_depth and depth != 1 << depth_bits:
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raise ValueError("AsyncFIFO only supports depths that are powers of 2; requested "
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"exact depth {} is not"
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.format(depth)) from None
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depth = 1 << depth_bits
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else:
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depth_bits = 0
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super().__init__(width=width, depth=depth)
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self.r_rst = Signal()
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self._r_domain = r_domain
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self._w_domain = w_domain
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self._ctr_bits = depth_bits + 1
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def elaborate(self, platform):
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m = Module()
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if self.depth == 0:
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m.d.comb += [
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self.w_rdy.eq(0),
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self.r_rdy.eq(0),
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]
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return m
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# The design of this queue is the "style #2" from Clifford E. Cummings' paper "Simulation
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# and Synthesis Techniques for Asynchronous FIFO Design":
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# http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
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do_write = self.w_rdy & self.w_en
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do_read = self.r_rdy & self.r_en
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# TODO: extract this pattern into lib.cdc.GrayCounter
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produce_w_bin = Signal(self._ctr_bits)
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produce_w_nxt = Signal(self._ctr_bits)
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m.d.comb += produce_w_nxt.eq(produce_w_bin + do_write)
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m.d[self._w_domain] += produce_w_bin.eq(produce_w_nxt)
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# Note: Both read-domain counters must be reset_less (see comments below)
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consume_r_bin = Signal(self._ctr_bits, reset_less=True)
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consume_r_nxt = Signal(self._ctr_bits)
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m.d.comb += consume_r_nxt.eq(consume_r_bin + do_read)
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m.d[self._r_domain] += consume_r_bin.eq(consume_r_nxt)
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produce_w_gry = Signal(self._ctr_bits)
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produce_r_gry = Signal(self._ctr_bits)
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produce_enc = m.submodules.produce_enc = \
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GrayEncoder(self._ctr_bits)
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produce_cdc = m.submodules.produce_cdc = \
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FFSynchronizer(produce_w_gry, produce_r_gry, o_domain=self._r_domain)
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m.d.comb += produce_enc.i.eq(produce_w_nxt),
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m.d[self._w_domain] += produce_w_gry.eq(produce_enc.o)
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consume_r_gry = Signal(self._ctr_bits, reset_less=True)
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consume_w_gry = Signal(self._ctr_bits)
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consume_enc = m.submodules.consume_enc = \
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GrayEncoder(self._ctr_bits)
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consume_cdc = m.submodules.consume_cdc = \
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FFSynchronizer(consume_r_gry, consume_w_gry, o_domain=self._w_domain)
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m.d.comb += consume_enc.i.eq(consume_r_nxt)
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m.d[self._r_domain] += consume_r_gry.eq(consume_enc.o)
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consume_w_bin = Signal(self._ctr_bits)
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consume_dec = m.submodules.consume_dec = \
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GrayDecoder(self._ctr_bits)
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m.d.comb += consume_dec.i.eq(consume_w_gry),
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m.d[self._w_domain] += consume_w_bin.eq(consume_dec.o)
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produce_r_bin = Signal(self._ctr_bits)
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produce_dec = m.submodules.produce_dec = \
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GrayDecoder(self._ctr_bits)
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m.d.comb += produce_dec.i.eq(produce_r_gry),
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m.d.comb += produce_r_bin.eq(produce_dec.o)
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w_full = Signal()
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r_empty = Signal()
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m.d.comb += [
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w_full.eq((produce_w_gry[-1] != consume_w_gry[-1]) &
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(produce_w_gry[-2] != consume_w_gry[-2]) &
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(produce_w_gry[:-2] == consume_w_gry[:-2])),
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r_empty.eq(consume_r_gry == produce_r_gry),
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]
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m.d[self._w_domain] += self.w_level.eq(produce_w_bin - consume_w_bin)
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m.d.comb += self.r_level.eq(produce_r_bin - consume_r_bin)
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storage = m.submodules.storage = Memory(width=self.width, depth=self.depth)
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w_port = storage.write_port(domain=self._w_domain)
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r_port = storage.read_port (domain=self._r_domain, transparent=False)
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m.d.comb += [
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w_port.addr.eq(produce_w_bin[:-1]),
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w_port.data.eq(self.w_data),
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w_port.en.eq(do_write),
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self.w_rdy.eq(~w_full),
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]
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m.d.comb += [
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r_port.addr.eq(consume_r_nxt[:-1]),
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self.r_data.eq(r_port.data),
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r_port.en.eq(1),
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self.r_rdy.eq(~r_empty),
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]
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# Reset handling to maintain FIFO and CDC invariants in the presence of a write-domain
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# reset.
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# There is a CDC hazard associated with resetting an async FIFO - Gray code counters which
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# are reset to 0 violate their Gray code invariant. One way to handle this is to ensure
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# that both sides of the FIFO are asynchronously reset by the same signal. We adopt a
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# slight variation on this approach - reset control rests entirely with the write domain.
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# The write domain's reset signal is used to asynchronously reset the read domain's
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# counters and force the FIFO to be empty when the write domain's reset is asserted.
|
|
# This requires the two read domain counters to be marked as "reset_less", as they are
|
|
# reset through another mechanism. See https://github.com/amaranth-lang/amaranth/issues/181
|
|
# for the full discussion.
|
|
w_rst = ResetSignal(domain=self._w_domain, allow_reset_less=True)
|
|
r_rst = Signal()
|
|
|
|
# Async-set-sync-release synchronizer avoids CDC hazards
|
|
rst_cdc = m.submodules.rst_cdc = \
|
|
AsyncFFSynchronizer(w_rst, r_rst, o_domain=self._r_domain)
|
|
|
|
# Decode Gray code counter synchronized from write domain to overwrite binary
|
|
# counter in read domain.
|
|
rst_dec = m.submodules.rst_dec = \
|
|
GrayDecoder(self._ctr_bits)
|
|
m.d.comb += rst_dec.i.eq(produce_r_gry)
|
|
with m.If(r_rst):
|
|
m.d.comb += r_empty.eq(1)
|
|
m.d[self._r_domain] += consume_r_gry.eq(produce_r_gry)
|
|
m.d[self._r_domain] += consume_r_bin.eq(rst_dec.o)
|
|
m.d[self._r_domain] += self.r_rst.eq(1)
|
|
with m.Else():
|
|
m.d[self._r_domain] += self.r_rst.eq(0)
|
|
|
|
if platform == "formal":
|
|
with m.If(Initial()):
|
|
m.d.comb += Assume(produce_w_gry == (produce_w_bin ^ produce_w_bin[1:]))
|
|
m.d.comb += Assume(consume_r_gry == (consume_r_bin ^ consume_r_bin[1:]))
|
|
|
|
return m
|
|
|
|
|
|
class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
|
|
__doc__ = FIFOInterface._doc_template.format(
|
|
description="""
|
|
Buffered asynchronous first in, first out queue.
|
|
|
|
Read and write interfaces are accessed from different clock domains, which can be set when
|
|
constructing the FIFO.
|
|
|
|
:class:`AsyncFIFOBuffered` only supports power of 2 plus one depths. Unless ``exact_depth``
|
|
is specified, the ``depth`` parameter is rounded up to the next power of 2 plus one.
|
|
(The output buffer acts as an additional queue element.)
|
|
|
|
This queue's interface is identical to :class:`AsyncFIFO`, but it has an additional register
|
|
on the output, improving timing in case of block RAM that has large clock-to-output delay.
|
|
|
|
In exchange, the latency between an entry being written to an empty queue and that entry
|
|
becoming available on the output is increased by one cycle compared to :class:`AsyncFIFO`.
|
|
""".strip(),
|
|
parameters="""
|
|
r_domain : str
|
|
Read clock domain.
|
|
w_domain : str
|
|
Write clock domain.
|
|
""".strip(),
|
|
attributes="",
|
|
r_data_valid="Valid if ``r_rdy`` is asserted.",
|
|
r_attributes="""
|
|
r_rst : Signal(1), out
|
|
Asserted, for at least one read-domain clock cycle, after the FIFO has been reset by
|
|
the write-domain reset.
|
|
""".strip(),
|
|
w_attributes="")
|
|
|
|
def __init__(self, *, width, depth, r_domain="read", w_domain="write", exact_depth=False):
|
|
if depth != 0:
|
|
depth_bits = ceil_log2(max(0, depth - 1))
|
|
if exact_depth and depth != (1 << depth_bits) + 1:
|
|
raise ValueError("AsyncFIFOBuffered only supports depths that are one higher "
|
|
"than powers of 2; requested exact depth {} is not"
|
|
.format(depth)) from None
|
|
depth = (1 << depth_bits) + 1
|
|
super().__init__(width=width, depth=depth)
|
|
|
|
self.r_rst = Signal()
|
|
self._r_domain = r_domain
|
|
self._w_domain = w_domain
|
|
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
if self.depth == 0:
|
|
m.d.comb += [
|
|
self.w_rdy.eq(0),
|
|
self.r_rdy.eq(0),
|
|
]
|
|
return m
|
|
|
|
m.submodules.unbuffered = fifo = AsyncFIFO(width=self.width, depth=self.depth - 1,
|
|
r_domain=self._r_domain, w_domain=self._w_domain)
|
|
|
|
m.d.comb += [
|
|
fifo.w_data.eq(self.w_data),
|
|
self.w_rdy.eq(fifo.w_rdy),
|
|
fifo.w_en.eq(self.w_en),
|
|
]
|
|
|
|
r_consume_buffered = Signal()
|
|
m.d.comb += r_consume_buffered.eq((self.r_rdy - self.r_en) & self.r_rdy)
|
|
m.d[self._r_domain] += self.r_level.eq(fifo.r_level + r_consume_buffered)
|
|
|
|
w_consume_buffered = Signal()
|
|
m.submodules.consume_buffered_cdc = FFSynchronizer(r_consume_buffered, w_consume_buffered, o_domain=self._w_domain, stages=4)
|
|
m.d.comb += self.w_level.eq(fifo.w_level + w_consume_buffered)
|
|
|
|
with m.If(self.r_en | ~self.r_rdy):
|
|
m.d[self._r_domain] += [
|
|
self.r_data.eq(fifo.r_data),
|
|
self.r_rdy.eq(fifo.r_rdy),
|
|
self.r_rst.eq(fifo.r_rst),
|
|
]
|
|
m.d.comb += [
|
|
fifo.r_en.eq(1)
|
|
]
|
|
|
|
return m
|