whitequark 12beda6e5b back.verilog: omit Verilog initial trigger only if Yosys adds it. ... Verilog has an edge case where an `always @*` process, which is used to describe a combinatorial function procedurally, may not execute at time zero because none of the signals in its implicit sensitivity list change, i.e. when the process doesn't read any signals. This causes the wires driven by the process to stay undefined. The workaround to this problem (assuming SystemVerilog `always_comb` is not available) is to introduce a dummy signal that changes only at time zero and is optimized out during synthesis. nMigen has had its own workaround, `$verilog_initial_trigger`, for a while. However, `proc_prune`, while increasing readability, pulls references to this signal out of the process. Because of this, a similar workaround was implemented in Yosys' `write_verilog` itself. This commit ensures we use our workaround on versions of Yosys without the updated `write_verilog`, and Yosys' workaround on later versions. Fixes #418.		2020-08-26 16:51:12 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
cxxrtl.py	back.cxxrtl: actualize Yosys version requirement.	2020-08-26 09:16:46 +00:00
pysim.py	back.pysim→sim.pysim; split into more manageable parts.	2020-07-08 12:49:38 +00:00
rtlil.py	back.rtlil: lower maximum accepted wire size.	2020-07-22 14:43:44 +00:00
verilog.py	back.verilog: omit Verilog initial trigger only if Yosys adds it.	2020-08-26 16:51:12 +00:00