539 lines
21 KiB
Python
539 lines
21 KiB
Python
import math
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from vcd import VCDWriter
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from vcd.gtkw import GTKWSave
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from ..tools import flatten
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from ..fhdl.ast import *
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from ..fhdl.xfrm import ValueTransformer, StatementTransformer
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__all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]
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class DeadlineError(Exception):
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pass
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class _State:
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__slots__ = ("curr", "curr_dirty", "next", "next_dirty")
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def __init__(self):
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self.curr = ValueDict()
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self.next = ValueDict()
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self.curr_dirty = ValueSet()
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self.next_dirty = ValueSet()
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def get(self, signal):
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return self.curr[signal]
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def set_curr(self, signal, value):
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assert isinstance(value, int)
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if self.curr[signal] != value:
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self.curr_dirty.add(signal)
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self.curr[signal] = value
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def set_next(self, signal, value):
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assert isinstance(value, int)
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if self.next[signal] != value:
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self.next_dirty.add(signal)
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self.next[signal] = value
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def commit(self, signal):
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old_value = self.curr[signal]
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if self.curr[signal] != self.next[signal]:
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self.next_dirty.remove(signal)
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self.curr_dirty.add(signal)
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self.curr[signal] = self.next[signal]
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new_value = self.curr[signal]
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return old_value, new_value
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def iter_dirty(self):
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dirty, self.dirty = self.dirty, ValueSet()
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for signal in dirty:
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yield signal, self.curr[signal], self.next[signal]
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normalize = Const.normalize
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class _RHSValueCompiler(ValueTransformer):
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def __init__(self, sensitivity):
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self.sensitivity = sensitivity
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def on_Const(self, value):
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return lambda state: value.value
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def on_Signal(self, value):
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self.sensitivity.add(value)
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return lambda state: state.get(value)
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def on_ClockSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_ResetSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_Operator(self, value):
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shape = value.shape()
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if len(value.operands) == 1:
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arg, = map(self, value.operands)
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if value.op == "~":
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return lambda state: normalize(~arg(state), shape)
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if value.op == "-":
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return lambda state: normalize(-arg(state), shape)
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elif len(value.operands) == 2:
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lhs, rhs = map(self, value.operands)
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if value.op == "+":
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return lambda state: normalize(lhs(state) + rhs(state), shape)
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if value.op == "-":
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return lambda state: normalize(lhs(state) - rhs(state), shape)
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if value.op == "&":
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return lambda state: normalize(lhs(state) & rhs(state), shape)
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if value.op == "|":
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return lambda state: normalize(lhs(state) | rhs(state), shape)
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if value.op == "^":
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return lambda state: normalize(lhs(state) ^ rhs(state), shape)
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if value.op == "==":
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return lambda state: normalize(lhs(state) == rhs(state), shape)
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elif len(value.operands) == 3:
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if value.op == "m":
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sel, val1, val0 = map(self, value.operands)
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return lambda state: val1(state) if sel(state) else val0(state)
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raise NotImplementedError("Operator '{}' not implemented".format(value.op))
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def on_Slice(self, value):
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shape = value.shape()
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arg = self(value.value)
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shift = value.start
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mask = (1 << (value.end - value.start)) - 1
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return lambda state: normalize((arg(state) >> shift) & mask, shape)
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def on_Part(self, value):
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raise NotImplementedError
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def on_Cat(self, value):
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shape = value.shape()
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parts = []
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offset = 0
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for opnd in value.operands:
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parts.append((offset, (1 << len(opnd)) - 1, self(opnd)))
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offset += len(opnd)
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def eval(state):
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result = 0
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for offset, mask, opnd in parts:
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result |= (opnd(state) & mask) << offset
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return normalize(result, shape)
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return eval
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def on_Repl(self, value):
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shape = value.shape()
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offset = len(value.value)
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mask = (1 << len(value.value)) - 1
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count = value.count
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opnd = self(value.value)
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def eval(state):
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result = 0
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for _ in range(count):
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result <<= offset
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result |= opnd(state)
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return normalize(result, shape)
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return eval
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class _StatementCompiler(StatementTransformer):
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def __init__(self):
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self.sensitivity = ValueSet()
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self.rhs_compiler = _RHSValueCompiler(self.sensitivity)
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def lhs_compiler(self, value):
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# TODO
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return lambda state, arg: state.set_next(value, arg)
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def on_Assign(self, stmt):
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assert isinstance(stmt.lhs, Signal)
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shape = stmt.lhs.shape()
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lhs = self.lhs_compiler(stmt.lhs)
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rhs = self.rhs_compiler(stmt.rhs)
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def run(state):
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lhs(state, normalize(rhs(state), shape))
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return run
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def on_Switch(self, stmt):
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test = self.rhs_compiler(stmt.test)
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cases = []
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for value, stmts in stmt.cases.items():
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if "-" in value:
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mask = "".join("0" if b == "-" else "1" for b in value)
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value = "".join("0" if b == "-" else b for b in value)
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else:
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mask = "1" * len(value)
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mask = int(mask, 2)
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value = int(value, 2)
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def make_test(mask, value):
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return lambda test: test & mask == value
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cases.append((make_test(mask, value), self.on_statements(stmts)))
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def run(state):
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test_value = test(state)
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for check, body in cases:
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if check(test_value):
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body(state)
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return
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return run
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def on_statements(self, stmts):
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stmts = [self.on_statement(stmt) for stmt in stmts]
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def run(state):
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for stmt in stmts:
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stmt(state)
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return run
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class Simulator:
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def __init__(self, fragment, vcd_file=None, gtkw_file=None, gtkw_signals=()):
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self._fragments = {} # fragment -> hierarchy
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self._domains = {} # str/domain -> ClockDomain
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self._domain_triggers = ValueDict() # Signal -> str/domain
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self._domain_signals = {} # str/domain -> {Signal}
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self._signals = ValueSet() # {Signal}
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self._comb_signals = ValueSet() # {Signal}
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self._sync_signals = ValueSet() # {Signal}
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self._user_signals = ValueSet() # {Signal}
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self._started = False
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self._timestamp = 0.
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self._epsilon = 1e-10
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self._fastest_clock = self._epsilon
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self._state = _State()
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self._processes = set() # {process}
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self._passive = set() # {process}
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self._suspended = set() # {process}
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self._wait_deadline = {} # process -> float/timestamp
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self._wait_tick = {} # process -> str/domain
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self._funclets = ValueDict() # Signal -> set(lambda)
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self._vcd_file = vcd_file
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self._vcd_writer = None
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self._vcd_signals = ValueDict() # signal -> set(vcd_signal)
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self._vcd_names = ValueDict() # signal -> str/name
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self._gtkw_file = gtkw_file
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self._gtkw_signals = gtkw_signals
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fragment = fragment.prepare()
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def add_fragment(fragment, hierarchy=("top",)):
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self._fragments[fragment] = hierarchy
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for subfragment, name in fragment.subfragments:
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add_fragment(subfragment, (*hierarchy, name))
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add_fragment(fragment)
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self._domains = fragment.domains
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for domain, cd in self._domains.items():
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self._domain_triggers[cd.clk] = domain
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if cd.rst is not None:
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self._domain_triggers[cd.rst] = domain
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self._domain_signals[domain] = ValueSet()
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def add_process(self, process):
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self._processes.add(process)
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def add_clock(self, domain, period):
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if self._fastest_clock == self._epsilon or period < self._fastest_clock:
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self._fastest_clock = period
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half_period = period / 2
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clk = self._domains[domain].clk
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def clk_process():
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yield Passive()
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yield Delay(half_period)
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while True:
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yield clk.eq(1)
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yield Delay(half_period)
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yield clk.eq(0)
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yield Delay(half_period)
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self.add_process(clk_process())
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def add_sync_process(self, process, domain="sync"):
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def sync_process():
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try:
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result = process.send(None)
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while True:
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result = process.send((yield (result or Tick(domain))))
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except StopIteration:
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pass
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self.add_process(sync_process())
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def __enter__(self):
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if self._vcd_file:
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self._vcd_writer = VCDWriter(self._vcd_file, timescale="100 ps",
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comment="Generated by nMigen")
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for fragment in self._fragments:
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for signal in fragment.iter_signals():
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self._signals.add(signal)
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self._state.curr[signal] = self._state.next[signal] = \
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normalize(signal.reset, signal.shape())
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self._state.curr_dirty.add(signal)
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if signal not in self._vcd_signals:
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self._vcd_signals[signal] = set()
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for subfragment, name in fragment.subfragments:
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if signal in subfragment.ports:
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var_name = "{}_{}".format(name, signal.name)
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break
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else:
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var_name = signal.name
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if signal.decoder:
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var_type = "string"
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var_size = 1
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var_init = signal.decoder(signal.reset).replace(" ", "_")
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else:
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var_type = "wire"
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var_size = signal.nbits
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var_init = signal.reset
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suffix = None
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while True:
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try:
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if suffix is None:
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var_name_suffix = var_name
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else:
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var_name_suffix = "{}${}".format(var_name, suffix)
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self._vcd_signals[signal].add(self._vcd_writer.register_var(
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scope=".".join(self._fragments[fragment]), name=var_name_suffix,
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var_type=var_type, size=var_size, init=var_init))
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if signal not in self._vcd_names:
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self._vcd_names[signal] = \
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".".join(self._fragments[fragment] + (var_name_suffix,))
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break
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except KeyError:
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suffix = (suffix or 0) + 1
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for domain, signals in fragment.drivers.items():
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if domain is None:
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self._comb_signals.update(signals)
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else:
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self._sync_signals.update(signals)
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self._domain_signals[domain].update(signals)
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statements = []
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for signal in fragment.iter_comb():
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statements.append(signal.eq(signal.reset))
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statements += fragment.statements
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def add_funclet(signal, funclet):
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if signal not in self._funclets:
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self._funclets[signal] = set()
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self._funclets[signal].add(funclet)
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compiler = _StatementCompiler()
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funclet = compiler(statements)
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for signal in compiler.sensitivity:
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add_funclet(signal, funclet)
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for domain, cd in fragment.domains.items():
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add_funclet(cd.clk, funclet)
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if cd.rst is not None:
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add_funclet(cd.rst, funclet)
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self._user_signals = self._signals - self._comb_signals - self._sync_signals
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def _update_dirty_signals(self):
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"""Perform the statement part of IR processes (aka RTLIL case)."""
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# First, for all dirty signals, use sensitivity lists to determine the set of fragments
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# that need their statements to be reevaluated because the signals changed at the previous
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# delta cycle.
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funclets = set()
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while self._state.curr_dirty:
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signal = self._state.curr_dirty.pop()
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if signal in self._funclets:
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funclets.update(self._funclets[signal])
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# Second, compute the values of all signals at the start of the next delta cycle, by
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# running precompiled statements.
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for funclet in funclets:
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funclet(self._state)
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def _commit_signal(self, signal, domains):
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"""Perform the driver part of IR processes (aka RTLIL sync), for individual signals."""
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# Take the computed value (at the start of this delta cycle) of a signal (that could have
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# come from an IR process that ran earlier, or modified by a simulator process) and update
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# the value for this delta cycle.
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old, new = self._state.commit(signal)
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# If the signal is a clock that triggers synchronous logic, record that fact.
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if (old, new) == (0, 1) and signal in self._domain_triggers:
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domains.add(self._domain_triggers[signal])
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if self._vcd_writer and old != new:
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# Finally, dump the new value to the VCD file.
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for vcd_signal in self._vcd_signals[signal]:
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if signal.decoder:
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var_value = signal.decoder(new).replace(" ", "_")
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else:
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var_value = new
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self._vcd_writer.change(vcd_signal, self._timestamp / self._epsilon, var_value)
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def _commit_comb_signals(self, domains):
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"""Perform the comb part of IR processes (aka RTLIL always)."""
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# Take the computed value (at the start of this delta cycle) of every comb signal and
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# update the value for this delta cycle.
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for signal in self._state.next_dirty:
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if signal in self._comb_signals or signal in self._user_signals:
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self._commit_signal(signal, domains)
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def _commit_sync_signals(self, domains):
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"""Perform the sync part of IR processes (aka RTLIL posedge)."""
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# At entry, `domains` contains a list of every simultaneously triggered sync update.
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while domains:
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# Advance the timeline a bit (purely for observational purposes) and commit all of them
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# at the same timestamp.
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self._timestamp += self._epsilon
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curr_domains, domains = domains, set()
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while curr_domains:
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domain = curr_domains.pop()
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# Take the computed value (at the start of this delta cycle) of every sync signal
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# in this domain and update the value for this delta cycle. This can trigger more
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# synchronous logic, so record that.
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for signal in self._state.next_dirty:
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if signal in self._domain_signals[domain]:
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self._commit_signal(signal, domains)
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# Wake up any simulator processes that wait for a domain tick.
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for process, wait_domain in list(self._wait_tick.items()):
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if domain == wait_domain:
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del self._wait_tick[process]
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self._suspended.remove(process)
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# Unless handling synchronous logic above has triggered more synchronous logic (which
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# can happen e.g. if a domain is clocked off a clock divisor in fabric), we're done.
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# Otherwise, do one more round of updates.
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def _run_process(self, process):
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try:
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stmt = process.send(None)
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except StopIteration:
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self._processes.remove(process)
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self._passive.discard(process)
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return
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if isinstance(stmt, Delay):
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self._wait_deadline[process] = self._timestamp + stmt.interval
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self._suspended.add(process)
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elif isinstance(stmt, Tick):
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self._wait_tick[process] = stmt.domain
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self._suspended.add(process)
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elif isinstance(stmt, Passive):
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self._passive.add(process)
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elif isinstance(stmt, Assign):
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lhs_signals = stmt.lhs._lhs_signals()
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for signal in lhs_signals:
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if not signal in self._signals:
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raise ValueError("Process {!r} sent a request to set signal '{!r}', "
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"which is not a part of simulation"
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.format(process, signal))
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if signal in self._comb_signals:
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raise ValueError("Process {!r} sent a request to set signal '{!r}', "
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"which is a part of combinatorial assignment in simulation"
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.format(process, signal))
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funclet = _StatementCompiler()(stmt)
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funclet(self._state)
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domains = set()
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for signal in lhs_signals:
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self._commit_signal(signal, domains)
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self._commit_sync_signals(domains)
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else:
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raise TypeError("Received unsupported statement '{!r}' from process {!r}"
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.format(stmt, process))
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def step(self, run_passive=False):
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deadline = None
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if self._wait_deadline:
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# We might run some delta cycles, and we have simulator processes waiting on
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# a deadline. Take care to not exceed the closest deadline.
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deadline = min(self._wait_deadline.values())
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# Are there any delta cycles we should run?
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while self._state.curr_dirty:
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self._timestamp += self._epsilon
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if deadline is not None and self._timestamp >= deadline:
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# Oops, we blew the deadline. We *could* run the processes now, but this is
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# virtually certainly a logic loop and a design bug, so bail out instead.d
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raise DeadlineError("Delta cycles exceeded process deadline; combinatorial loop?")
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domains = set()
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self._update_dirty_signals()
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self._commit_comb_signals(domains)
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self._commit_sync_signals(domains)
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# Are there any processes that haven't had a chance to run yet?
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if len(self._processes) > len(self._suspended):
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# Schedule an arbitrary one.
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process = (self._processes - set(self._suspended)).pop()
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self._run_process(process)
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return True
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# All processes are suspended. Are any of them active?
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if len(self._processes) > len(self._passive) or run_passive:
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# Are any of them suspended before a deadline?
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if self._wait_deadline:
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# Schedule the one with the lowest deadline.
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process, deadline = min(self._wait_deadline.items(), key=lambda x: x[1])
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del self._wait_deadline[process]
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self._suspended.remove(process)
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self._timestamp = deadline
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self._run_process(process)
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return True
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# No processes, or all processes are passive. Nothing to do!
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return False
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def run_until(self, deadline, run_passive=False):
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while self._timestamp < deadline:
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if not self.step(run_passive):
|
|
return False
|
|
|
|
return True
|
|
|
|
def __exit__(self, *args):
|
|
if self._vcd_writer:
|
|
self._vcd_writer.close(self._timestamp / self._epsilon)
|
|
|
|
if self._vcd_file and self._gtkw_file:
|
|
gtkw_save = GTKWSave(self._gtkw_file)
|
|
if hasattr(self._vcd_file, "name"):
|
|
gtkw_save.dumpfile(self._vcd_file.name)
|
|
if hasattr(self._vcd_file, "tell"):
|
|
gtkw_save.dumpfile_size(self._vcd_file.tell())
|
|
|
|
gtkw_save.treeopen("top")
|
|
gtkw_save.zoom_markers(math.log(self._epsilon / self._fastest_clock) - 14)
|
|
|
|
for domain, cd in self._domains.items():
|
|
with gtkw_save.group("d.{}".format(domain)):
|
|
if cd.rst is not None:
|
|
gtkw_save.trace(self._vcd_names[cd.rst])
|
|
gtkw_save.trace(self._vcd_names[cd.clk])
|
|
|
|
for signal in self._gtkw_signals:
|
|
if signal in self._vcd_names:
|
|
if len(signal) > 1:
|
|
suffix = "[{}:0]".format(len(signal) - 1)
|
|
else:
|
|
suffix = ""
|
|
gtkw_save.trace(self._vcd_names[signal] + suffix)
|