Thomas Watson c7f719ab93 hdl.ast: allow Signals to be privately named using name="" ... * Given a private name `$\d+` in RTLIL (as they are not named in the IR) * Not automatically added to VCD files (as they are not named in the IR) * Cannot be traced to a VCD (as they have no name to put in the file) * Cannot be used with an unnamed top-level port (as there is no name)		2024-03-25 19:15:24 +00:00
..
__init__.py	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
_base.py	sim: allow visualizing delta cycles in VCD dumps.	2024-03-24 12:07:49 +00:00
_pyclock.py	sim: represent time internally as 1ps units	2021-12-13 08:15:11 +00:00
_pycoro.py	sim: write process commands to VCD file.	2024-03-24 12:21:32 +00:00
_pyrtl.py	Implement RFC 53: Low-level I/O primitives.	2024-03-18 20:33:22 +00:00
core.py	hdl.ast: allow Signals to be privately named using name=""	2024-03-25 19:15:24 +00:00
pysim.py	sim: write process commands to VCD file.	2024-03-24 12:21:32 +00:00