1f10bd96b9
This also reorganizes README to more clearly describe what nMigen is, since it was getting quite outdated.
68 lines
2.2 KiB
Python
68 lines
2.2 KiB
Python
from .. import tracer
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from .ast import Signal
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__all__ = ["ClockDomain", "DomainError"]
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class DomainError(Exception):
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pass
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class ClockDomain:
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"""Synchronous domain.
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Parameters
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----------
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name : str or None
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Domain name. If ``None`` (the default) the name is inferred from the variable name this
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``ClockDomain`` is assigned to (stripping any `"cd_"` prefix).
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reset_less : bool
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If ``True``, the domain does not use a reset signal. Registers within this domain are
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still all initialized to their reset state once, e.g. through Verilog `"initial"`
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statements.
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async_reset : bool
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If ``True``, the domain uses an asynchronous reset, and registers within this domain
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are initialized to their reset state when reset level changes. Otherwise, registers
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are initialized to reset state at the next clock cycle when reset is asserted.
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Attributes
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----------
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clk : Signal, inout
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The clock for this domain. Can be driven or used to drive other signals (preferably
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in combinatorial context).
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rst : Signal or None, inout
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Reset signal for this domain. Can be driven or used to drive.
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"""
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@staticmethod
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def _name_for(domain_name, signal_name):
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if domain_name == "sync":
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return signal_name
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else:
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return "{}_{}".format(domain_name, signal_name)
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def __init__(self, name=None, reset_less=False, async_reset=False):
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if name is None:
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try:
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name = tracer.get_var_name()
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except tracer.NameNotFound:
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raise ValueError("Clock domain name must be specified explicitly")
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if name.startswith("cd_"):
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name = name[3:]
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self.name = name
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self.clk = Signal(name=self._name_for(name, "clk"), src_loc_at=1)
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if reset_less:
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self.rst = None
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else:
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self.rst = Signal(name=self._name_for(name, "rst"), src_loc_at=1)
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self.async_reset = async_reset
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def rename(self, new_name):
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self.name = new_name
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self.clk.name = self._name_for(new_name, "clk")
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if self.rst is not None:
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self.rst.name = self._name_for(new_name, "rst")
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