361 lines
13 KiB
Python
361 lines
13 KiB
Python
from abc import abstractproperty
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from ..hdl import *
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from ..build import *
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__all__ = ["LatticeECP5Platform"]
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class LatticeECP5Platform(TemplatedPlatform):
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"""
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Required tools:
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* ``yosys``
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* ``nextpnr-ecp5``
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* ``ecppack``
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Available overrides:
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* ``verbose``: enables logging of informational messages to standard error.
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* ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
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* ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
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* ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
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* ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
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* ``yosys_opts``: adds extra options for Yosys.
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* ``nextpnr_opts``: adds extra options for nextpnr.
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* ``ecppack_opts``: adds extra options for ecppack.
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Build products:
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* ``{{name}}.rpt``: Yosys log.
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* ``{{name}}.json``: synthesized RTL.
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* ``{{name}}.tim``: nextpnr log.
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* ``{{name}}.config``: ASCII bitstream.
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* ``{{name}}.bit``: binary bitstream.
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* ``{{name}}.svf``: JTAG programming vector.
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"""
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device = abstractproperty()
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package = abstractproperty()
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speed = abstractproperty()
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_nextpnr_device_options = {
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"LFE5U-12F": "--25k",
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"LFE5U-25F": "--25k",
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"LFE5U-45F": "--45k",
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"LFE5U-85F": "--85k",
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"LFE5UM-12F": "--um-25k",
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"LFE5UM-25F": "--um-25k",
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"LFE5UM-45F": "--um-45k",
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"LFE5UM-85F": "--um-85k",
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"LFE5UM5G-12F": "--um5g-25k",
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"LFE5UM5G-25F": "--um5g-25k",
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"LFE5UM5G-45F": "--um5g-45k",
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"LFE5UM5G-85F": "--um5g-85k",
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}
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_nextpnr_package_options = {
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"BG256": "caBGA256",
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"MG285": "csfBGA285",
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"BG381": "caBGA381",
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"BG554": "caBGA554",
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"BG756": "caBGA756",
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}
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file_templates = {
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**TemplatedPlatform.build_script_templates,
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"{{name}}.il": r"""
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# {{autogenerated}}
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{{emit_design("rtlil")}}
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""",
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"{{name}}.ys": r"""
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# {{autogenerated}}
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{% for file in platform.iter_extra_files(".v") -%}
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read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
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{% endfor %}
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{% for file in platform.iter_extra_files(".sv") -%}
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read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
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{% endfor %}
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read_ilang {{name}}.il
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{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
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synth_ecp5 {{get_override("synth_opts")|join(" ")}} -top {{name}}
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{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
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write_json {{name}}.json
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""",
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"{{name}}.lpf": r"""
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# {{autogenerated}}
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BLOCK ASYNCPATHS;
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BLOCK RESETPATHS;
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{% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
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LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
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IOBUF PORT "{{port_name}}"
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{%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
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{% endfor %}
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{% for signal, frequency in platform.iter_clock_constraints() -%}
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FREQUENCY PORT "{{signal.name}}" {{frequency}} HZ;
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{% endfor %}
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"""
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}
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command_templates = [
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r"""
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{{get_tool("yosys")}}
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{{quiet("-q")}}
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{{get_override("yosys_opts")|join(" ")}}
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-l {{name}}.rpt
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{{name}}.ys
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""",
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r"""
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{{get_tool("nextpnr-ecp5")}}
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{{quiet("--quiet")}}
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{{get_override("nextpnr_opts")|join(" ")}}
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--log {{name}}.tim
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{{platform._nextpnr_device_options[platform.device]}}
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--package {{platform._nextpnr_package_options[platform.package]|upper}}
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--speed {{platform.speed}}
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--json {{name}}.json
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--lpf {{name}}.lpf
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--textcfg {{name}}.config
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""",
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r"""
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{{get_tool("ecppack")}}
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{{verbose("--verbose")}}
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--input {{name}}.config
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--bit {{name}}.bit
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--svf {{name}}.svf
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"""
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]
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_single_ended_io_types = [
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"HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
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"SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
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]
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_differential_io_types = [
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"BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
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"LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
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"SLVS", "SSTL135D_II", "SSTL15D_II", "SSTL18D_II", "SUBLVDS",
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]
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def should_skip_port_component(self, port, attrs, component):
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# On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
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# the PIOA or PIOC location, which is always the non-inverting pin.
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if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
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return True
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return False
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def _get_xdr_buffer(self, m, pin, i_invert=None, o_invert=None):
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def get_ireg(clk, d, q):
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for bit in range(len(q)):
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m.submodules += Instance("IFS1P3DX",
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i_SCLK=clk,
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=d[bit],
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o_Q=q[bit]
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)
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def get_oreg(clk, d, q):
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for bit in range(len(q)):
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m.submodules += Instance("OFS1P3DX",
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i_SCLK=clk,
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=d[bit],
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o_Q=q[bit]
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)
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def get_iddr(sclk, d, q0, q1):
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for bit in range(len(d)):
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m.submodules += Instance("IDDRX1F",
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i_SCLK=sclk,
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i_RST=Const(0),
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i_D=d[bit],
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o_Q0=q0[bit], o_Q1=q1[bit]
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)
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def get_oddr(sclk, d0, d1, q):
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for bit in range(len(q)):
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m.submodules += Instance("ODDRX1F",
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i_SCLK=sclk,
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i_RST=Const(0),
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i_D0=d0[bit], i_D1=d1[bit],
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o_Q=q[bit]
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)
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def get_ixor(z, invert):
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if invert is None:
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return z
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else:
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a = Signal.like(z, name_suffix="_x{}".format(1 if invert else 0))
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for bit in range(len(z)):
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m.submodules += Instance("LUT4",
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p_INIT=0x5555 if invert else 0xaaaa,
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i_A=a[bit],
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o_Z=z[bit]
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)
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return a
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def get_oxor(a, invert):
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if invert is None:
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return a
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else:
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z = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
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for bit in range(len(a)):
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m.submodules += Instance("LUT4",
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p_INIT=0x5555 if invert else 0xaaaa,
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i_A=a[bit],
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o_Z=z[bit]
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)
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return z
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_ixor(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_ixor(pin.i0, i_invert)
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pin_i1 = get_ixor(pin.i1, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = get_oxor(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = get_oxor(pin.o0, o_invert)
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pin_o1 = get_oxor(pin.o1, o_invert)
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i = o = t = None
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if "i" in pin.dir:
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i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
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if "o" in pin.dir:
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o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
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if pin.dir in ("oe", "io"):
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t = Signal(1, name="{}_xdr_t".format(pin.name))
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if pin.xdr == 0:
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if "i" in pin.dir:
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i = pin_i
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if "o" in pin.dir:
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o = pin_o
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if pin.dir in ("oe", "io"):
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t = ~pin_oe
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elif pin.xdr == 1:
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# Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
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if "i" in pin.dir:
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get_ireg(pin.i_clk, i, pin_i)
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if "o" in pin.dir:
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get_oreg(pin.o_clk, pin_o, o)
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if pin.dir in ("oe", "io"):
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get_oreg(pin.o_clk, ~pin.oe, t)
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elif pin.xdr == 2:
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if "i" in pin.dir:
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get_iddr(pin.i_clk, i, pin_i0, pin_i1)
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if "o" in pin.dir:
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get_oddr(pin.o_clk, pin_o0, pin_o1, o)
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if pin.dir in ("oe", "io"):
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# It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
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# It is not clear what is the recommended set of primitives for this task.
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# Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
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get_oreg(pin.o_clk, ~pin.oe, t)
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else:
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assert False
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return (i, o, t)
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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t, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
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for bit in range(len(port)):
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m.submodules += Instance("IB",
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i_I=port[bit],
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o_O=i[bit]
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)
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
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for bit in range(len(port)):
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m.submodules += Instance("OB",
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i_I=o[bit],
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o_O=port[bit]
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)
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return m
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
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for bit in range(len(port)):
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m.submodules += Instance("OBZ",
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i_T=t,
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i_I=o[bit],
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o_O=port[bit]
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)
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return m
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
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o_invert=True if invert else None)
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for bit in range(len(port)):
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m.submodules += Instance("BB",
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i_T=t,
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i_I=o[bit],
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o_O=i[bit],
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io_B=port[bit]
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)
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
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for bit in range(len(p_port)):
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m.submodules += Instance("IB",
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i_I=p_port[bit],
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o_O=i[bit]
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)
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return m
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def get_diff_output(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
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for bit in range(len(p_port)):
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m.submodules += Instance("OB",
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i_I=o[bit],
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o_O=p_port[bit],
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)
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return m
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def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
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for bit in range(len(p_port)):
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m.submodules += Instance("OBZ",
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i_T=t,
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i_I=o[bit],
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o_O=p_port[bit],
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)
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return m
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def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
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o_invert=True if invert else None)
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for bit in range(len(p_port)):
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m.submodules += Instance("BB",
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i_T=t,
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i_I=o[bit],
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o_O=i[bit],
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io_B=p_port[bit],
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)
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return m
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