whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None. ... Fixes #164.		2019-08-03 12:30:39 +00:00
..
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
ast.py	hdl.{ast,dsl},back.rtlil: track source locations for switch cases.	2019-07-09 19:26:47 +00:00
cd.py	hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.	2019-07-08 10:26:49 +00:00
dsl.py	hdl.dsl: add getters to m.submodules.	2019-07-19 12:39:47 +00:00
ir.py	hdl.ir: warn if .elaborate() returns None.	2019-08-03 12:30:39 +00:00
mem.py	hdl.{dsl,mem,xfrm}: inject appropriate source locations.	2019-07-08 09:58:12 +00:00
rec.py	hdl.rec: respect modifications to signals in Record.like().	2019-07-08 10:59:15 +00:00
xfrm.py	hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.	2019-07-31 05:20:05 +00:00