323 lines
13 KiB
Python
323 lines
13 KiB
Python
from abc import abstractproperty
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import os
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import subprocess
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import tempfile
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from ...hdl import *
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from ...build import *
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__all__ = ["LatticeICE40Platform",
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"IceStormProgrammerMixin", "IceBurnProgrammerMixin", "TinyProgrammerMixin"]
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class LatticeICE40Platform(TemplatedPlatform):
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"""
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Required tools:
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* ``yosys``
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* ``nextpnr-ice40``
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* ``icepack``
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Available overrides:
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* ``verbose``: enables logging of informational messages to standard error.
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* ``read_opts``: adds options for ``read`` Yosys command.
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* ``synth_opts``: adds options for ``synth_ice40`` Yosys command.
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* ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
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* ``script_after_synth``: inserts commands after ``synth_ice40`` in Yosys script.
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* ``yosys_opts``: adds extra options for Yosys.
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* ``nextpnr_opts``: adds extra and overrides default options (``--placer heap``)
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for nextpnr.
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Build products:
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* ``{{name}}.rpt``: Yosys log.
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* ``{{name}}.json``: synthesized RTL.
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* ``{{name}}.tim``: nextpnr log.
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* ``{{name}}.asc``: ASCII bitstream.
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* ``{{name}}.bin``: binary bitstream.
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"""
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device = abstractproperty()
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package = abstractproperty()
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file_templates = {
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**TemplatedPlatform.build_script_templates,
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"{{name}}.il": r"""
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# {{autogenerated}}
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{{emit_design("rtlil")}}
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""",
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"{{name}}.ys": r"""
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# {{autogenerated}}
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{% for file in platform.extra_files %}
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{% if file.endswith(".v") -%}
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read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
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{% elif file.endswith(".sv") -%}
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read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
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{% endif %}
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{% endfor %}
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read_ilang {{name}}.il
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{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
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synth_ice40 {{get_override("synth_opts")|join(" ")}} -top {{name}}
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{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
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write_json {{name}}.json
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""",
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"{{name}}.pcf": r"""
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# {{autogenerated}}
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{% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
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set_io {{port_name}} {{pin_name}}
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{% endfor %}
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""",
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"{{name}}_pre_pack.py": r"""
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# {{autogenerated}}
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{% for port, frequency in platform.iter_clock_constraints() -%}
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{# Clock in MHz #}
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ctx.addClock("{{port}}", {{frequency/1000000}})
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{% endfor%}
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""",
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}
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command_templates = [
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r"""
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{{get_tool("yosys")}}
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{{quiet("-q")}}
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{{get_override("yosys_opts")|join(" ")}}
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-l {{name}}.rpt
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{{name}}.ys
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""",
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r"""
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{{get_tool("nextpnr-ice40")}}
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{{quiet("-q")}}
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{{get_override("nextpnr_opts")|default(["--placer","heap"])|join(" ")}}
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-l {{name}}.tim
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--{{platform.device}}
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--package {{platform.package}}
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--json {{name}}.json
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--pcf {{name}}.pcf
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--pre-pack {{name}}_pre_pack.py
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--asc {{name}}.asc
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""",
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r"""
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{{get_tool("icepack")}}
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{{verbose("-v")}}
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{{name}}.asc
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{{name}}.bin
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"""
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]
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def iter_ports(self):
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for res, pin, port in self._ports:
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if isinstance(res.io[0], Pins):
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yield port.io
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elif isinstance(res.io[0], DiffPairs):
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if res.extras.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT":
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yield port.p
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else:
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yield port.p
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yield port.n
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else:
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assert False
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def iter_port_constraints(self):
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for res, pin, port in self._ports:
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if isinstance(res.io[0], Pins):
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yield port.io.name, list(res.io[0].map_names(self._mapping, res)), res.extras
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elif isinstance(res.io[0], DiffPairs):
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if res.extras.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT":
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yield port.p.name, list(res.io[0].p.map_names(self._mapping, res)), res.extras
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else:
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yield port.p.name, list(res.io[0].p.map_names(self._mapping, res)), res.extras
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yield port.n.name, list(res.io[0].n.map_names(self._mapping, res)), res.extras
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else:
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assert False
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def _get_io_buffer(self, m, pin, port, extras, o_invert=None):
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def _get_dff(clk, d, q):
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m.submodules += Instance("$dff",
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p_CLK_POLARITY=0,
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p_WIDTH=len(d),
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i_CLK=clk,
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i_D=d,
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o_Q=q)
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def _get_inverter(a, invert):
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if invert is None:
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return a
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else:
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y = Signal.like(a, name="{}_x{}".format(a.name, 1 if invert else 0))
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for bit in range(len(a)):
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m.submodules += Instance("SB_LUT4",
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p_LUT_INIT=0b01 if invert else 0b10,
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i_I0=a[bit],
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i_I1=Const(0),
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i_I2=Const(0),
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i_I3=Const(0),
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o_O=y[bit])
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return y
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if "GLOBAL" in extras:
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is_global_input = bool(extras["GLOBAL"])
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del extras["GLOBAL"]
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else:
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is_global_input = False
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = _get_inverter(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = _get_inverter(pin.o0, o_invert)
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pin_o1 = _get_inverter(pin.o1, o_invert)
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if "i" in pin.dir and pin.xdr == 2:
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i0_ff = Signal.like(pin.i0, name="{}_ff".format(pin.i0.name))
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i1_ff = Signal.like(pin.i1, name="{}_ff".format(pin.i1.name))
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_get_dff(pin.i_clk, i0_ff, pin.i0)
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_get_dff(pin.i_clk, i1_ff, pin.i1)
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if "o" in pin.dir and pin.xdr == 2:
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o1_ff = Signal.like(pin.o1, name="{}_ff".format(pin.o1.name))
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_get_dff(pin.o_clk, pin_o1, o1_ff)
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for bit in range(len(port)):
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io_args = [
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("io", "PACKAGE_PIN", port[bit]),
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*(("p", key, value) for key, value in extras.items()),
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]
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if "i" not in pin.dir:
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i_type = 0b00 # PIN_NO_INPUT aka PIN_INPUT_REGISTERED
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elif pin.xdr == 0:
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i_type = 0b01 # PIN_INPUT
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elif pin.xdr > 0:
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i_type = 0b00 # PIN_INPUT_REGISTERED
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if "o" not in pin.dir:
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o_type = 0b0000 # PIN_NO_OUTPUT
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elif pin.xdr == 0 and pin.dir == "o":
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o_type = 0b0110 # PIN_OUTPUT
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elif pin.xdr == 0:
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o_type = 0b1010 # PIN_OUTPUT_TRISTATE
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elif pin.xdr == 1 and pin.dir == "o":
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o_type = 0b0101 # PIN_OUTPUT_REGISTERED
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elif pin.xdr == 1:
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o_type = 0b1101 # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
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elif pin.xdr == 2 and pin.dir == "o":
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o_type = 0b0100 # PIN_OUTPUT_DDR
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elif pin.xdr == 2:
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o_type = 0b1100 # PIN_OUTPUT_DDR_ENABLE_REGISTERED
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io_args.append(("p", "PIN_TYPE", (o_type << 2) | i_type))
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if hasattr(pin, "i_clk"):
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io_args.append(("i", "INPUT_CLK", pin.i_clk))
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if hasattr(pin, "o_clk"):
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io_args.append(("i", "OUTPUT_CLK", pin.o_clk))
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if "i" in pin.dir:
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if pin.xdr == 0 and is_global_input:
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io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", pin.i[bit]))
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elif pin.xdr < 2:
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io_args.append(("o", "D_IN_0", pin.i[bit]))
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elif pin.xdr == 2:
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# Re-register both inputs before they enter fabric. This increases hold time
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# to an entire cycle, and adds one cycle of latency.
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io_args.append(("o", "D_IN_0", i0_ff))
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io_args.append(("o", "D_IN_1", i1_ff))
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if "o" in pin.dir:
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if pin.xdr < 2:
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io_args.append(("i", "D_OUT_0", pin_o[bit]))
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elif pin.xdr == 2:
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# Re-register negedge output after it leaves fabric. This increases setup time
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# to an entire cycle, and doesn't add latency.
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io_args.append(("i", "D_OUT_0", pin_o0[bit]))
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io_args.append(("i", "D_OUT_1", o1_ff))
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if pin.dir in ("oe", "io"):
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io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
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if is_global_input:
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m.submodules += Instance("SB_GB_IO", *io_args)
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else:
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m.submodules += Instance("SB_IO", *io_args)
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def get_input(self, pin, port, extras):
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self._check_feature("single-ended input", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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return m
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def get_output(self, pin, port, extras):
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self._check_feature("single-ended output", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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return m
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def get_tristate(self, pin, port, extras):
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self._check_feature("single-ended tristate", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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return m
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def get_input_output(self, pin, port, extras):
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self._check_feature("single-ended input/output", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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return m
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def get_diff_input(self, pin, p_port, n_port, extras):
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self._check_feature("differential input", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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# On iCE40, a differential input is placed by only instantiating an SB_IO primitive for
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# the pin with z=0, which is the non-inverting pin. The pinout unfortunately differs
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# between LP/HX and UP series:
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# * for LP/HX, z=0 is DPxxB (B is non-inverting, A is inverting)
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# * for UP, z=0 is IOB_xxA (A is non-inverting, B is inverting)
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m = Module()
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self._get_io_buffer(m, pin, p_port, extras)
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return m
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def get_diff_output(self, pin, p_port, n_port, extras):
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self._check_feature("differential output", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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m = Module()
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# Note that the non-inverting output pin is not driven the same way as a regular
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# output pin. The inverter introduces a delay, so for a non-inverting output pin,
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# an identical delay is introduced by instantiating a LUT. This makes the waveform
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# perfectly symmetric in the xdr=0 case.
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self._get_io_buffer(m, pin, p_port, extras, o_invert=False)
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self._get_io_buffer(m, pin, n_port, extras, o_invert=True)
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return m
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# Tristate and bidirectional buffers are not supported on iCE40 because it requires external
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# termination, which is incompatible for input and output differential I/Os.
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class IceStormProgrammerMixin:
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def toolchain_program(self, products, name, *, mode=None):
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if mode is None and hasattr(self, "prog_mode"):
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mode = self.prog_mode
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if mode not in ("sram", "flash"):
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raise ValueError("iceprog mode must be one of \"sram\" or \"flash\", not {!r}; "
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"specify it using .build(..., program_opts={\"mode\": \"<mode>\"})"
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.format(mode))
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iceprog = os.environ.get("ICEPROG", "iceprog")
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if mode == "sram":
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options = ["-S"]
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if mode == "flash":
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options = []
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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subprocess.run([iceprog, *options, bitstream_filename], check=True)
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class IceBurnProgrammerMixin:
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def toolchain_program(self, products, name):
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iceburn = os.environ.get("ICEBURN", "iCEburn")
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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subprocess.run([iceburn, "-evw", bitstream_filename], check=True)
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class TinyProgrammerMixin:
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def toolchain_program(self, products, name):
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tinyprog = os.environ.get("TINYPROG", "tinyprog")
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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subprocess.run([tinyprog, "-p", bitstream_filename], check=True)
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