a2241fcfdb
Because Fragment.prepare is not (currently) idempotent, it is useful to be able to avoid calling it when converting. Even if it is made idempotent, it can be slow on large designs, so it is advantageous regardless of that.
32 lines
991 B
Python
32 lines
991 B
Python
import warnings
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from ...hdl.ir import Fragment
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from ...hdl.cd import ClockDomain
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from ...back import verilog
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from .conv_output import ConvOutput
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def convert(fi, ios=None, name="top", special_overrides=dict(),
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attr_translate=None, create_clock_domains=True,
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display_run=False):
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if display_run:
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warnings.warn("`display_run=True` support has been removed",
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DeprecationWarning, stacklevel=1)
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if special_overrides:
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warnings.warn("`special_overrides` support as well as `Special` has been removed",
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DeprecationWarning, stacklevel=1)
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# TODO: attr_translate
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def missing_domain(name):
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if create_clock_domains:
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return ClockDomain(name)
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v_output = verilog.convert(
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elaboratable=fi.get_fragment(),
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name=name,
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ports=ios or (),
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missing_domain=missing_domain
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)
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output = ConvOutput()
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output.set_main_source(v_output)
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return output
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