|
alu.py
|
fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
|
2018-12-12 12:38:24 +00:00 |
|
alu_hier.py
|
fhdl.ir: fix port threading code.
|
2018-12-12 13:00:50 +00:00 |
|
arst.py
|
fhdl.ir: implement clock domain propagation.
|
2018-12-13 11:01:03 +00:00 |
|
clkdiv.py
|
back.pysim: more general clean-up.
|
2018-12-14 12:46:04 +00:00 |
|
ctrl.py
|
back.pysim: Simulator({gtkw_signals→traces}=).
|
2018-12-14 15:23:22 +00:00 |
